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hc05 MC68HC05F8D/h mc68hc05f8 mc68hc705f8 technical data !motorola mc68hc05f8 !motorola technical data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 general description pin descriptions memory and registers resets interrupts timers serial peripheral interface manchester encoder/decoder dtmf/melody generator cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications tpg 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 general description pin descriptions memory and registers resets interrupts timers serial peripheral interface manchester encoder/decoder dtmf/melody generator cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications tpg 2
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tpg 4 conventions register and bit mnemonics are de?ed in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ? is used to indicate an unde?ed state (on reset).
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mc68hc05f8 motorola i paragraph number page number title table of contents 1 general description 1.1 features.................................................................................................................1-1 1.1.1 hardware features ..........................................................................................1-1 1.1.2 software features............................................................................................1-2 2 pin descriptions 2.1 functional pin descriptions ...................................................................................2-1 2.2 pin assignments ....................................................................................................2-3 2.3 input/output programming ....................................................................................2-4 2.3.1 parallel ports....................................................................................................2-4 2.3.2 serial port (spi) ...............................................................................................2-4 3 memory and registers 3.1 memory map..........................................................................................................3-1 3.2 input/output section ..............................................................................................3-1 3.3 ram.......................................................................................................................3-1 4 resets 4.1 power-on reset (por) .........................................................................................4-1 4.2 reset pin ............................................................................................................4-1 4.3 illegal address (iladr) reset...............................................................................4-2 4.4 computer operating properly (cop) reset ..........................................................4-2 tpg 7
motorola ii mc68hc05f8 paragraph number page number title 5 interrupts 5.1 hardware controlled sequences...........................................................................5-4 5.2 software interrupt (swi)........................................................................................5-4 5.3 external interrupts (irq1 & irq2 ) ........................................................................5-4 5.3.1 external interrupt triggering options (intn1 & intn2) ..................................5-6 5.3.2 external interrupt enable (inte1 & inte2).....................................................5-6 5.3.3 external interrupt flags (intf1 & intf2) .......................................................5-7 5.4 keyboard interrupt.................................................................................................5-7 5.4.1 keyboard control register...............................................................................5-8 5.5 programmable timer (timer a) interrupt...............................................................5-8 5.6 reloadable timer (timer b) interrupt ....................................................................5-10 5.7 spi interrupt ..........................................................................................................5-10 5.8 manchester coder (mancd) interrupt..................................................................5-11 6 timers 6.1 timer a - programmable timer ..................................................................6-1 6.1.1 counter ............................................................................................................6-1 6.1.2 output compare registers ..............................................................................6-4 6.1.3 input capture registers...................................................................................6-4 6.1.4 timer control register (tcr)..........................................................................6-5 6.1.5 timer a status register (tsr) ........................................................................6-6 6.1.6 programmable timer timing diagrams ...........................................................6-7 6.2 timer b - reloadable timer .........................................................................6-10 6.2.1 functional description .....................................................................................6-10 6.2.2 resolution and maximum period .....................................................................6-10 6.2.3 timer b counter ..............................................................................................6-11 6.2.4 timer b preset register ..................................................................................6-12 6.2.5 timer b control status register ......................................................................6-12 6.3 cop watchdog .................................................................................................6-13 6.3.1 watchdog timer time-out flag .......................................................................6-13 6.3.2 cop system enable and operation ................................................................6-14 6.3.3 disable cop function in stop or wait mode ...................................................6-14 6.3.4 watchdog timer control status register (wdcsr)........................................6-14 7 serial peripheral interface 7.1 features ................................................................................................................7-1 7.2 signal description .................................................................................................7-1 7.2.1 serial clock (sck)...........................................................................................7-2 tpg 8
mc68hc05f8 motorola iii paragraph number page number title 7.2.2 serial data output (sdo) ................................................................................7-3 7.2.3 serial data input (sdi).....................................................................................7-3 7.3 general operation .................................................................................................7-3 7.4 spi registers.........................................................................................................7-3 7.4.1 spi control register (spcr)...........................................................................7-4 7.4.2 spi status register (spsr) ............................................................................7-5 7.4.3 serial peripheral data register (spdr) ..........................................................7-6 8 manchester encoder/decoder 8.1 features.................................................................................................................8-1 8.2 general operation .................................................................................................8-2 8.2.1 encoder............................................................................................................8-2 8.2.1.1 idle state of encoder..................................................................................8-3 8.2.1.2 initialization of encoder ..............................................................................8-3 8.2.1.3 encode data register empty flag (ncm) and encode interrupt...............8-3 8.2.1.4 end pattern generation and next data byte encoding..............................8-3 8.2.1.5 disable encoder .........................................................................................8-3 8.2.2 decoder ...........................................................................................................8-5 8.2.2.1 decoder overrun........................................................................................8-5 8.2.2.2 data bit format error detection .................................................................8-6 8.2.2.3 bit rate error detection .............................................................................8-6 8.3 manchester encoder/decoder registers...............................................................8-6 8.3.1 mancd control register.................................................................................8-6 8.3.2 mancd status register ..................................................................................8-8 8.3.3 encode data register ($2d)............................................................................8-9 8.3.4 decode data register ($2e)............................................................................8-9 9 dtmf/melody generator 9.1 features.................................................................................................................9-1 9.2 general operation .................................................................................................9-1 9.3 dmg registers ......................................................................................................9-3 9.3.1 row frequency control register (fcr) column frequency control register (fcc) .....................................................9-3 9.3.2 tone control register (tncr) .........................................................................9-4 9.4 programming the dmg..........................................................................................9-6 9.4.1 dtmf dialling ..................................................................................................9-6 9.4.2 melody generation...........................................................................................9-6 9.4.3 tonex generation ............................................................................................9-6 9.4.4 melody+tonex generation..............................................................................9-6 tpg 9
motorola iv mc68hc05f8 paragraph number page number title 10 cpu core and instruction set 10.1 registers .............................................................................................................10-1 10.1.1 accumulator (a) .............................................................................................10-1 10.1.2 index register (x) ...........................................................................................10-2 10.1.3 program counter (pc)....................................................................................10-2 10.1.4 stack pointer (sp)..........................................................................................10-2 10.1.5 condition code register (ccr).......................................................................10-2 10.2 instruction set ......................................................................................................10-3 10.2.1 register/memory instructions ........................................................................10-4 10.2.2 branch instructions ........................................................................................10-4 10.2.3 bit manipulation instructions ..........................................................................10-4 10.2.4 read/modify/write instructions.......................................................................10-4 10.2.5 control instructions ........................................................................................10-4 10.2.6 tables.............................................................................................................10-4 10.3 addressing modes...............................................................................................10-11 10.3.1 inherent..........................................................................................................10-11 10.3.2 immediate ......................................................................................................10-11 10.3.3 direct .............................................................................................................10-11 10.3.4 extended........................................................................................................10-12 10.3.5 indexed, no offset ..........................................................................................10-12 10.3.6 indexed, 8-bit offset .......................................................................................10-12 10.3.7 indexed, 16-bit offset .....................................................................................10-12 10.3.8 relative ..........................................................................................................10-13 10.3.9 bit set/clear ....................................................................................................10-13 10.3.10 bit test and branch.........................................................................................10-13 11 low power modes 11.1 stop mode ...........................................................................................................11-1 11.1.1 timer a during stop mode.............................................................................11-1 11.1.2 timer b during stop mode.............................................................................11-2 11.1.3 spi during stop mode....................................................................................11-2 11.1.4 dmg during stop mode .................................................................................11-2 11.1.5 cop during stop mode..................................................................................11-2 11.2 wait mode ...........................................................................................................11-3 12 operating modes 12.1 user mode (normal operation) ...........................................................................12-2 12.2 self-check mode .................................................................................................12-2 tpg 10
mc68hc05f8 motorola v paragraph number page number title 12.3 bootstrap mode ...................................................................................................12-4 12.3.1 eprom program control register ................................................................12-4 12.3.2 eprom programming sequence ..................................................................12-5 12.3.3 program and verify eprom ..........................................................................12-6 12.3.4 verify eprom contents.................................................................................12-7 13 electrical specifications 13.1 maximum ratings ................................................................................................13-1 13.2 thermal characteristics.......................................................................................13-1 13.3 dc electrical characteristics ...............................................................................13-2 13.4 dtmf/melody generator electrical characteristics ............................................13-4 13.5 control timing .....................................................................................................13-5 13.6 programming operation electrical characteristics ..............................................13-7 14 mechanical specifications 14.1 56-pin sdip package...........................................................................................14-1 14.2 64-pin qfp package............................................................................................14-2 tpg 11
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mc68hc05f8 motorola vii figure number page number title list of figures 1-1 mc68hc05f8/mc68hc705f8 block diagram ......................................................1-3 2-1 pin assignments for 56-pin sdip package.............................................................2-3 2-2 pin assignments for 64-pin qfp package..............................................................2-3 2-3 parallel port i/o circuitry ........................................................................................2-5 3-1 mc68hc05f8/mc68hc705f8 memory map ........................................................3-2 4-1 power-on reset and reset timing......................................................................4-4 5-1 interrupt stacking order .........................................................................................5-2 5-2 hardware interrupt flowchart .................................................................................5-3 5-3 external interrupt circuit and timing ......................................................................5-5 5-4 keyboard interrupt circuit.......................................................................................5-9 6-1 programmable timer block diagram......................................................................6-2 6-2 timer state timing diagram for reset ...................................................................6-8 6-3 timer state timing diagram for input capture .......................................................6-8 6-4 timer state timing diagram for output compare ..................................................6-9 6-5 timer state diagram for timer over?w ................................................................6-9 6-6 reloadable timer block diagram ...........................................................................6-11 6-7 watchdog timer block diagram .............................................................................6-13 7-1 spi master-slave interconnection ..........................................................................7-2 7-2 spi port timing.......................................................................................................7-2 7-3 spi block diagram..................................................................................................7-4 8-1 manchester encoder/decoder block diagram........................................................8-2 8-2 logic flow of encoder hardware operation...........................................................8-4 8-3 encoder timing diagram ........................................................................................8-5 8-4 logic flow of decoder hardware operation...........................................................8-7 9-1 dtmf/melody generator block diagram ...............................................................9-2 10-1 programming model .............................................................................................10-1 10-2 stacking order ......................................................................................................10-2 12-1 flowchart of mode entering .................................................................................12-1 12-2 self-check mode timing ......................................................................................12-2 12-3 self-test circuit ....................................................................................................12-3 12-4 eprom programming sequence.........................................................................12-6 12-5 eprom programming circuit for bootstrap mode ...............................................12-7 14-1 56-pin sdip mechanical dimensions ...................................................................14-1 14-2 64-pin qfp mechanical dimensions ....................................................................14-2 tpg 13
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mc68hc05f8 motorola ix ta b l e number page number title list of tables 2-1 i/o pin functions ....................................................................................................2-4 3-1 mc68hc05f8/ mc68hc705f8 registers ..............................................................3-3 4-1 reset action on internal circuit ..............................................................................4-3 5-1 reset/interrupt vector addresses ..........................................................................5-2 6-1 timer a clock frequency selection .......................................................................6-3 6-2 reloadable timer resolution and maximum period...............................................6-10 9-1 bit description for dtmf generation .....................................................................9-3 9-2 bit description for melody generation....................................................................9-4 9-3 dmg operating modes...........................................................................................9-5 9-4 effect of tone generation enable on dmg.............................................................9-5 10-1 mul instruction.....................................................................................................10-5 10-2 register/memory instructions...............................................................................10-5 10-3 branch instructions ...............................................................................................10-6 10-4 bit manipulation instructions.................................................................................10-6 10-5 read/modify/write instructions .............................................................................10-7 10-6 control instructions...............................................................................................10-7 10-7 instruction set .......................................................................................................10-8 10-8 m68hc05 opcode map.........................................................................................10-10 12-1 mode selection.....................................................................................................12-2 12-2 self-check report ................................................................................................12-4 12-3 bootstrap mode options.......................................................................................12-4 13-1 dc electrical characteristics for 5v operation ....................................................13-2 13-2 dc electrical characteristics for 2.7v operation .................................................13-3 13-3 electrical speci?ation of sine wave tones at toneout output..........................13-4 13-4 electrical speci?ation of square wave tones at toneout output .....................13-4 13-5 electrical speci?ation of tonex at tonex output ..............................................13-4 13-6 control timing for 5v operation ...........................................................................13-5 13-7 control timing for 2.7v operation ........................................................................13-6 tpg 15
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mc68hc05f8 motorola 1-1 general description 1 1 general description the mc68hc05f8 hcmos microcontroller is a member of the m68hc05 family of low-cost single-chip microcontrollers. this 8-bit microcontroller unit (mcu) contains an on-chip oscillator, cpu, ram, rom, i/o, timer, serial peripheral interface, manchester encoder/decoder, dtmf/melody generator, and cop watchdog monitor. this mcu is particularly suitable for cordless telephones with an answering machine. the mc68hc705f8 is an eprom version of the mc68hc05f8. all references to the mc68hc05f8 apply equally to the mc68hc705f8, unless otherwise stated. references speci? to the mc68hc705f8 are italicized in the text. 1.1 features the following are some of the hardware and software features of the mc68hc05f8 single-chip microcontroller. 1.1.1 hardware features hcmos technology 8-bit architecture power saving wait and stop modes full static operation 2.5v to 6v operating voltage 320 bytes of on-chip ram (64 bytes for stack) 8k-bytes of on-chip rom; 8k-bytes of on-chip eprom for mc68hc705f8 496-bytes self-check rom; 496-bytes bootstrap rom for mc68hc705f8 8 keyboard interrupt lines tpg 17
motorola 1-2 mc68hc05f8 general description 1 manchester encoder/decoder dtmf/melody generator oscillator for 3.579mhz crystal 16-bit free-running programmable timer with 4 selectable prescaler frequencies 16-bit auto-reload timer with 4 selectable prescaler frequencies computer operating properly (cop) watchdog monitor serial peripheral interface 10ma high current output pins for led direct driving available in 56-pin sdip and 64-pin qfp packages 1.1.2 software features similar to mc6800 8 x 8 unsigned multiply instruction ef?ient use of program space versatile interrupt handling true bit manipulation addressing modes with index addressing for tables ef?ient instruction set memory mapped i/o two power saving standby modes upward software compatible with the m146805 cmos family tpg 18
mc68hc05f8 motorola 1-3 general description 1 figure 1-1 mc68hc05f8/mc68hc705f8 block diagram user rom/ eprom - 8k-bytes self-check/ bootstrap rom - 496 bytes ram - 320 bytes accumulator index register stack pointer program counter condition code register m68hc05 cpu reset 0 7 0 0 0 0 15 7 7 15 4 5 0 0 0 0 0 0 0 01 1 1 1 1 hinzc osc ? 2 power 16-bit reloadable timer osc1 osc2 vdd vss spi pd5/sdi pd6/sdo pd7/sck pg0 pg1 irq1 irq2 pa0 - pa7 8 tcmp tcap cop system 16-bit free-running timer manchester encoder/decoder dtmf/melody generator ddr a port a pb0 - pb7 8 ddr b port b pc0 - pc7 8 ddr c port c ddr d port d pe0 - pe7 8 ddr e port e pf0 - pf7 8 ddr f port f ddr g port g pd0 - pd4 5 keyboard interrupt circuit encoout decoin toneout tonex timer/bus clock prescaler to peripherals tpg 19
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mc68hc05f8 motorola 2-1 pin descriptions 2 2 pin descriptions this section provides a description of the functional pins and i/o programming of the mc68hc05f8/ mc68hc705f8 microcontroller. 2.1 functional pin descriptions pin name 56-pin sdip pin no. 64-pin qfp pin no. description vdd, vss 53, 52 52, 51 power is supplied to the mcu using these two pins. vdd is power and vss is ground. irq 1 irq 2 10 9 2 1 irq1 and irq2 are software programmable to provide two choices of interrupt triggering sensitivity. these options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-sensitive and level sensitive triggering. reset 34 30 the active low reset input is not required for start-up, but can be used to reset the mcu internal state and provide an orderly software start-up procedure. tcap 49 48 the tcap input controls the input capture feature for the on-chip programmable free-running timer. tcmp 48 47 the tcmp pin provides an output for the output compare feature of the on-chip programmable free-running timer. osc1, osc2 33, 32 29, 28 these pins provide connections to the on-chip oscillator. the crystal frequency is 3.579545mhz. osc1 may be driven by an external oscillator if an external crystal circuit is not used. pa0-pa7 (pa4-pa7 only) 14-11 10-3 these eight i/o lines comprise port a. the state of any pin is software programmable. all port a lines are con?ured as input during power on or external reset. port a can also be programmed as keyboard interrupts. pa0 to pa3 are not bonded out on the 56-pin package. pb0-pb7 22-15 18-11 these eight i/o lines comprise port b. the state of any pin is software programmable. all port b lines are con?ured as input during power on or external reset. pc0-pc7 5-1, 56-54 60-53 these eight i/o lines comprise port c. the state of any pin is software programmable. all port c lines are con?ured as input during power on or external reset. each port c pins also has the ability to sink a maximum current of 10ma with a maximum saturation of 1v. tpg 21
motorola 2-2 mc68hc05f8 pin descriptions 2 pd0-pd7 sdi sdo sck (pd0-pd4 only) 47-43 - - - 46-39 41 40 39 these eight i/o lines comprise port d. the state of any pin is software programmable. all port d lines are con?ured as input during power on or external reset. when the spe bit of the spi control register (bit 6 of address $10) is set, pd5, pd6, & pd7 are used for sdi, sdo, & sck respectively, for the serial peripheral interface. pd5 to pd7 are not bonded out on the 56-pin package. hence, the 56-pin package does not have spi features. pe0-pe7 30-23 26-19 these eight i/o lines comprise port e. the state of any pin is software programmable. all port e lines are con?ured as input during power on or external reset. pf0-pf7 42-35 38-31 these eight i/o lines comprise port f. the state of any pin is software programmable. all port f lines are con?ured as input during power on or external reset. pg0, pg1 (pg0 only) 8 64, 63 these two i/o lines comprise port g. the state of any pin is software programmable. all port g lines are con?ured as input during power on or external reset. pg1 is not bonded out on the 56-pin package. encoout 6 61 this pin is for encoded data output from the manchester encoder. decoin 7 62 this pin is for raw (manchester) data input to the manchester decoder. toneout 50 49 this output pin provides dual tone dtmf or melody under the control of the dtmf/melody generator. tonex 51 50 this output pin provides paci?r tones under the control of the dtmf/melody generator. nc/ vpp 31 27 this pin is used as the programming voltage pin for the eprom version, mc68hc705f8. it is connected to vdd for normal operation. this pin is not used in the standard rom part, mc68hc05f8. pin name 56-pin sdip pin no. 64-pin qfp pin no. description tpg 22
mc68hc05f8 motorola 2-3 pin descriptions 2 2.2 pin assignments figure 2-1 pin assignments for 56-pin sdip package figure 2-2 pin assignments for 64-pin qfp package 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pc4 pc3 pc2 pc1 pc0 encoout decoin pg0 irq2 irq1 pa7 pa6 pa5 pa4 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pe7 pe6 pe5 pe4 pe3 pe2 pc5 pc6 pc7 vdd vss tonex toneout tcap tcmp pd0 pd1 pd2 pd3 pd4 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset osc1 osc2 nc/ vpp pe0 pe1 32 30 29 31 pc6 pc5 pc3 17 18 20 21 22 23 24 25 26 27 29 30 31 32 19 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 46 tcap tcmp pd1 pd2 pd3 pd4 pd5/sdi pd6/sdo pd7/sck pf0 pf1 pf2 pf3 pf4 pf5 pd0 irq 2 irq 1 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pa7 pb1 pb0 pe6 pe5 pe4 pe3 pe1 pe0 nc/ vpp osc2 osc1 reset pf7 pf6 pe7 pg0 pg1 encoout pc0 pc1 pc2 pc4 pc7 vdd vss tonex toneout decoin 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 pe2 28 64 63 61 60 59 58 56 55 54 53 52 51 50 49 62 57 tpg 23
motorola 2-4 mc68hc05f8 pin descriptions 2 2.3 input/output programming 2.3.1 parallel ports port a, b, c, d, e, f and g may be programmed as an input or an output under software control. the direction of the pins is determined by the state of corresponding bit in the port data direction register (ddr). each 8-bit port (except port g, where it has only 2 bits) has an associated 8-bit data direction register. any port a, b, c, d, e, f or g pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, which con?ure all port a, b, c, d, e, f and g pins as inputs. the data direction registers are capable of being written to or read by the processor. refer to figure 2-3 and table 2-1. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. 2.3.2 serial port (spi) the serial peripheral interface (spi) uses the port d pins for its function. the spi function requires three of the pins (pd5-pd7) for its serial data input (sdi), serial data output (sdo), and system clock (sck) respectively. see section 7 for detailed description of spi. table 2-1 i/o pin functions r/w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. tpg 24
mc68hc05f8 motorola 2-5 pin descriptions 2 figure 2-3 parallel port i/o circuitry input register bit input i/o output i/o pin data direction register bit latched output data bit internal mc68hc05 connections ddr 7 ddr 6 ddr 5 ddr 4 ddr 3 ddr 2 ddr 1 ddr 0 0 1 2 3 4 5 6 7 px7 px6 px5 px4 px3 px2 px1 px0 typical port data direction register typical port register i/o port lines & + v dd pad ip port data port ddr internal logic p n note: (1) ip = input protection (2) latch-up protection not shown (a) (b) (c) tpg 25
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mc68hc05f8 motorola 3-1 memory and registers 3 3 memory and registers this section describes the organization of the on-chip memory. 3.1 memory map the cpu can address 64k-bytes of memory space. the rom portion of memory holds the program instructions, ?ed data, user-de?ed vectors, and interrupt service routines. the ram portion of memory holds variable data. i/o registers are memory-mapped so that the cpu can access their locations in the same way that it accesses all other memory locations. figure 3-1 shows the memory map for the mc68hc05f8/ mc68hc705f8 . 3.2 input/output section the ?st 64 addresses of memory space, $0000-$003f, are the i/o section. these are the addresses of the i/o control registers, status registers, and data registers. 3.3 ram the 320 addresses from $0040-$017f are ram locations. the cpu uses the 64 ram addresses, $00c0-$00ff, as the stack. before processing an interrupt, the cpu uses ?e bytes of the stack to save the contents of the cpu registers. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. once the stack pointer passes $00c0, it wraps round back to $00ff. tpg 27
motorola 3-2 mc68hc05f8 memory and registers 3 figure 3-1 mc68hc05f8/ mc68hc705f8 memory map port g data register port a direction register port b direction register port c direction register port d direction register port a data register port b data register port c data register port d data register port e data register port f data register port e direction register port f direction register port g direction register reserved reserved serial peripheral control register serial peripheral status register serial peripheral data i/o register row frequency control register column frequency control register tone control register event enable register miscellaneous timer a control register timer a status register timer a input capture high register timer a input capture low register timer a output compare high register timer a output compare low register timer a counter high register timer a alternative counter high register timer b control register timer b preset counter high register timer b preset counter low register timer b counter low register timer b alternative counter high register timer b alternative counter low register reserved reserved manchester coder control register manchester coder status register manchester encoder register manchester decoder register reserved reserved reserved keyboard control register system option register watchdog timer control register reserved reserved reserved reserved reserved reserved reserved erpom programming control register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3a $3b $3c $3d $3e $3f $0000 timer b keyboard manchester coder spi timer a timer b irq swi reset $fff0 $fff2 $fff4 $fff6 $fff8 $fffa $fffc $fffe ports 14 bytes reserved 2 bytes spi 3 bytes dmg 3 bytes event enable miscellaneous 1 byte timer a 10 bytes reserved 2 bytes manchester coder reserved 5 bytes keyboard 1 byte system option watchdog timer 1 byte reserved 8 bytes i/o 64 bytes ram 128 bytes stack 64 bytes unused unused self-check/ bootstrap 496 bytes self-check/ bootstrap 16 bytes ram 128 bytes user vectors 16 bytes 63 0 $003f $00ff $0100 $0180 $02ff $0300 $fdff $fe00 $ffdf $ffe0 $ffef $fff0 $ffff $017f 0 63 383 384 767 768 65023 65024 65503 65504 255 256 65519 65520 65535 timer a counter low register timer a alternative counter low register timer b counter high register reserved reserved reserved 1 byte 4 bytes 7 bytes 1 byte user rom/ eprom 8192 bytes $ddef $de00 56831 56832 $0040 64 program vectors eprom pcr 1 byte tpg 28
mc68hc05f8 motorola 3-3 memory and registers 3 table 3-1 mc68hc05f8/ mc68hc705f8 registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00 port a data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01 part b data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02 port c data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $03 port d data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $04 port e data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $05 port f data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $06 port g data bit 1 bit 0 $07 port a data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $08 port b data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $09 port c data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $0a port d data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $0b port e data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $0c port f data direction ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 $0d port g data direction ddr1 ddr0 $0e not used $0f not used $10 spi control spie spe mstr $11 spi status spif dcol $12 spi data i/o $13 row frequency control fcr4 fcr3 fcr2 fcr1 fcr0 $14 column frequency control fcc4 fcc3 fcc2 fcc1 fcc0 $15 tone control ms1 ms0 tger tgec $16 event enable timh inte1 inte2 $17 miscellaneous por intf1 intf2 keyf $18 timer a control icie ocie toie iedg olvl $19 timer a status icf ocf tof $1a timer a input capture high $1b timer a input capture low $1c timer a output compare high $1d timer a output compare low $1e timer a counter high $1f timer a counter low tpg 29
motorola 3-4 mc68hc05f8 memory and registers 3 $20 timer a alternative counter high $21 timer a alternative counter low $22 timer b control tmbe tboie tcsb1 tcsb0 tuf $23 timer b preset counter high $24 timer b preset counter low $25 timer b counter high $26 timer b counter low $27 timer b alternative counter high $28 timer b alternative counter low $29 not used $2a not used $2b manchester coder control nce nie cie dce die br1 br0 $2c manchester coder status ncm ncc dcf ovf $2d manchester encoder data $2e manchester decoder data $2f not used $30 reserved $31 not used $32 not used $33 not used $34 keyboard control keye keyx7 keyx6 keyx5 keyx4 $35 system option tcsa1 tcsa0 intn1 intn2 $36 watchdog timer control wdte wdte kwdt wdtof wdt1 wdt0 $37 not used $38 not used $39 not used $3a not used $3b not used $3c reserved $3d reserved $3e not used $3f eprom programming control lat epgm table 3-1 mc68hc05f8/ mc68hc705f8 registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tpg 30
mc68hc05f8 motorola 4-1 resets 4 4 resets the mc68hc05f8 can be reset in four ways: by the initial power-on reset function, by an active low input to the reset pin, by an opcode fetch from an illegal address, and by a cop watchdog reset (if the watchdog timer is enabled). any of these resets will cause the program to go to its starting address, speci?d by the contents of memory locations $fffe and $ffff, and cause the interrupt mask of the condition code register to be set. 4.1 power-on reset (por) the power-on reset occurs when a positive transition is detected on the supply voltage, v dd . the power-on reset is used strictly for power-up conditions, and should not be used to detect any drops in the power supply voltage. there is no provision for a power-down reset. the power-on circuitry provides for a 4064 tcyc delay from the time that the oscillator becomes active. if the external reset pin is low at the end of the 4064 tcyc time out, the processor remains in the reset condition until reset goes high. the user must ensure that v dd has risen to a point where the mcu can operate properly prior to the time the 4064 por cycles have elapsed. if there is doubt, the external reset pin should remain low until such time that v dd has risen to the minimum operating voltage speci?d. after a power-on reset the por bit in the miscellaneous register (bit 7 of address $17) is set, indicating the reset was cause by a power-on, not cop watchdog time-out or external reset. the por bit is cleared by writing a logic ? to the bit. the por cannot be set by software. 4.2 reset pin the reset input pin is used to reset the mcu to provide an orderly software start-up procedure. when using the external reset, the reset pin must stay low for a minimum of 1.5tcyc. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. tpg 31
motorola 4-2 mc68hc05f8 resets 4 4.3 illegal address (iladr) reset the mcu monitors all opcode fetches. if an illegal address space is accessed during an opcode fetch, an internal reset is generated. illegal address spaces consist of all unused locations within the memory map and the i/o registers (see figure 3-1). because the internal reset signal is used, the mcu comes out of an iladr reset in the same operating mode it was in when the opcode was fetched. 4.4 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a speci? amount of time by a program reset sequence. note: cop time-out is prevented by periodically writing a logic 1 to bit 7 of address $36. if the watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop time-out was generated. the watchdog timer is initially disabled after a reset, it is enabled by writing a ? to bit 7 of address $36. once enabled, it cannot be disabled by software. refer to section 6.3 for detailed description of the cop watchdog system. table 4-1 shows the internal circuit actions on reset, but not necessary in order of occurrence. tpg 32
mc68hc05f8 motorola 4-3 resets 4 table 4-1 reset action on internal circuit default conditions after reset 1 timer a not inhibited (timha bit cleared). 2 timer a prescaler reset to zero state. 3 timer a counter con?ures to $fffc. 4 timer a output compare (tcmp) bit is reset to zero. 5 timer a clock=internal bus clock ? 4 (tcsa1=tcsa0=0). 6 all timer a interrupt enable bits cleared (icie, ocie, and toie) to disable timer interrupts. the olvl timer bit is also cleared by reset. 7 timer b is disabled (tmbe bit cleared). 8 timer b prescaler reset to zero (tcsb0=tcsb1=0). 9 all data direction registers cleared to zero (default as inputs). 10 stack pointer con?ured to $00ff. 11 internal address bus forced to restart vector ($fffe-$ffff). 12 i bit of condition code register set to logic 1. 13* stop latch cleared. 14 wait latch cleared. 15 external interrupt latch cleared (intf1=intf2=0). 16 external interrupt enable bits cleared (inte1 & inte2). 17 spi disabled (serial output enable control bit spe=0). other spi bits cleared are spie, mstr, spif, and dcol. 18 spi system con?ured to slave mode (mstr=0). 19 keyboard interrupt enabled (keye) and keyboard interrupt ?g (keyf) bits are cleared. 20 disable mancd (ncd=dce=0). 21 disable tone generation in dmg (tger=tgec=0). 22 place dmg in dtmf mode (ms1=ms0=0). 23 watchdog timer is inhibited (wdte=0), kill function is disabled (kwdt=0). 24 if reset is by por, set por bit. * indicates that time-out still occurs. listed numbers do not represent order of occurrence. tpg 33
motorola 4-4 mc68hc05f8 resets 4 figure 4-1 power-on reset and reset timing vdd osc1 pin 1 internal clock 2 internal address bus 2 internal data bus 2 reset fffe ffff new pc fffe fffe ffff t vddr vdd threshold (typically 1-2v) 4064 t cyc t oxov t cyc 3 new pch new pcl op code t rl =1.5t cyc pch pcl op code new pc notes: 1. osc1 is not meant to represent frequency. it is only used to represent time. 2. internal clock, internal address bus, and internal data bus signals are not available externally. 3. next rising edge of internal clock after rising edge of reset initiates reset sequence. tpg 34
mc68hc05f8 motorola 5-1 interrupts 5 5 interrupts the mc68hc05f8 is capable of handling eight types of interrupt, seven hardware and one software. the interrupt mask bit (? bit in the condition code register), if set, masks all interrupts except the software interrupt, swi. interrupts such as irq, timers, and mancd have several ?gs which will cause the interrupt. interrupt ?gs are found in ?ead only status registers, while their enables are in associated control registers. they are never mixed in the same register. if the enable bit is ?? it masks the interrupt from occurring but does not inhibit the ?g from being set. a reset clears all enable bits. the general sequence for clearing an interrupt is a software sequence of reading the status register while the ?g is set followed by a read or write of an associated register. when any of these interrupts occur, and if enabled, normal processing is suspended at the end of the current instruction execution. the state of the machine is pushed onto the stack (see figure 5-1 for stacking order) and the appropriate vector points to the starting address of the interrupt service routine (see table 5-1). also, the interrupt mask bit in the condition code register is set. this masks further interrupts. at the completion of the service routine, the software normally contains an rti instruction which, when executed, restores the machine state and continues executing the interrupted program. figure 5-2 is a ?wchart showing the program ?w and interrupt priority for hardware interrupts. note: the interrupt mask bit (i bit) will be cleared if and only if the corresponding bit stored on the stack is zero. tpg 35
motorola 5-2 mc68hc05f8 interrupts 5 figure 5-1 interrupt stacking order table 5-1 reset/interrupt vector addresses register flag name interrupt cpu interrupt vector address reset reset $fffe-$ffff software swi $fffc-$fffd miscellaneous intf 1 external interrupt 1 irq $fffa-$fffb intf 2 external interrupt 2 timer b control & status tuf timer under?w timer b $fff8-$fff9 timer a status icf input capture timer a $fff6-$fff7 ocf output compare tof timer over?w spi status spif spi interrupt spi $fff4-$fff5 mancd status ncm encoder data register empty manchester coder $fff2-$fff3 ncc encoder completion dcf decoder data register full ovf overrun interrupt miscellaneous keyf keyboard kb $fff0-$fff1 condition code register accumulator index register program counter (high byte) program counter (low byte) $00c0 (bottom of stack) $00c1 $00c2 $00fd $00fe $00ff (top of stack) unstacking 1 2 3 4 5 5 4 3 2 1 stacking order order tpg 36
mc68hc05f8 motorola 5-3 interrupts 5 figure 5-2 hardware interrupt flowchart from reset is i bit set ? irqx external interrupt ? timer b under?w interrupt ? interrupt ? timer a internal spi internal interrupt ? interrupt ? manchester encoder/decoder interrupt ? keyboard external fetch next instruction execute instruction set i bit stack pc, x, a, ccr load pc from interrupt vectors complete interrupt routine and execute rti y n y y y y y y n n n n n n tpg 37
motorola 5-4 mc68hc05f8 interrupts 5 5.1 hardware controlled sequences the following three functions are not strictly interrupts, however, they are tied very closely to the interrupts. these functions are reset , stop, wait. 1) reset the reset input pin causes the program to go to its starting address. this address is speci?d by the contents of memory locations $fffe and $ffff. the interrupt mask of the condition code register is also set. most parts of the mcu is con?ured to some known state as described in table 4-1. 2) stop the stop instruction causes the oscillator to be turned off and the processor ?leeps until an external interrupt (irq ), keyboard interrupt, or reset occurs. see section 11 on low power modes. 3) wait the wait instruction causes all processor clocks to stop, but leaves the timer a, timer b, mancd and spi clocks running. this ?est state of the processor can be exited by reset , an external interrupt (irq ), keyboard interrupt, timer or spi interrupt. there are no special wait vectors for these individual interrupts. see section 11 on low power modes. 5.2 software interrupt (swi) the software interrupt is an executable instruction. the action of the swi instruction is similar to the hardware interrupts. the swi is executed regardless of the state of the interrupt mask in the condition code register. the service routine address is speci?d by the contents of memory location $fffc and $fffd. 5.3 external interrupts (irq1 & irq2 ) the external interrupts irq1 and irq2 can be software con?ured for ?egative-edge or ?egative-edge and level sensitive triggering. when the signal of the external interrupt pin, irq1 or irq2 , satis?s the condition selected by the intn1 and intn2 bit in the system option register (bits 4 & 3 of address $35), an external interrupt occurs, and the appropriate intf ?g will be set. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is speci?d by the contents of $fffa & $fffb for both irq1 & irq2 . after servicing the interrupt, ?gs are cleared by writing a logic ? to the corresponding ?g; otherwise the cpu will keep servicing the interrupt. tpg 38
mc68hc05f8 motorola 5-5 interrupts 5 figure 5-3 external interrupt circuit and timing + & + external request interrupt power on reset external reset write ? to clear intfx d c r q q v dd irqx i bit (cc) irqx t ilih t ilil edge sensitive trigger condition the minimum pulse width t ilih is either 140ns (v dd =5v) or 280ns (v dd =3v). the period t ilil should not be less than the number of tcyc cycles it takes to ex- ecute the interrupt service routine plus 21 tcyc cycles. interrupt pin t ilil wired ored interrupt signals irq (mcu) if after servicing an interrupt the external interrupt pins remain low, then the next interrupt is recognized. normally used with wired or connection. (b) interrupt mode diagram (a) interrupt function diagram level sensitive trigger condition irqi irqn + irqx sensitivity option intnx intfx bit tpg 39
motorola 5-6 mc68hc05f8 interrupts 5 the interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt lines. figure 5-3 shows both a block diagram and timing for the interrupt lines (irq1 , irq2 ) to the processor. the ?st method is used if pulses on the interrupt line are spaced far enough apart to be serviced. the minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. once a pulse occurs, the next pulse should not occur until the mcu software has exited the routine (an rti occurs). the second con?uration shows several interrupt lines wired-or to perform the interrupt at the processor. thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. note: the internal interrupt latch is cleared in the ?st part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t ilil and serviced as soon as the i bit is cleared. 5.3.1 external interrupt triggering options (intn1 & intn2) intn1 1 (set) negative edge triggering for irq1 only. 0 (clear) level and negative edge triggering for irq1 . intn2 1 (set) negative triggering for irq2 only. 0 (clear) level and negative edge triggering for irq2 . 5.3.2 external interrupt enable (inte1 & inte2) int1e 1 (set) external interrupt irq1 enabled. 0 (clear) external interrupt irq1 disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset system option register $35 tcsa1 tcsa0 intn1 intn2 -000 0--- address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset event enable register $16 timha int1e int2e 000- ---- tpg 40
mc68hc05f8 motorola 5-7 interrupts 5 int2e 1 (set) external interrupt irq2 enabled. 0 (clear) external interrupt irq2 disabled. 5.3.3 external interrupt flags (intf1 & intf2) intf1 1 (set) an interrupt on irq1 pin has occurred. 0 (clear) an interrupt on irq1 pin has not occurred. after servicing this interrupt, this ?g should be cleared by writing a ? to this bit. intf2 1 (set) an interrupt on irq2 pin has occurred. 0 (clear) an interrupt on irq2 pin has not occurred. after servicing this interrupt, this ?g should be cleared by writing a ? to this bit. 5.4 keyboard interrupt port pins pa0-pa7 can be con?ured as keyboard interrupt lines with internal pull-up when the control bits keye, keyx4, keyx5, keyx6, and keyx7 are set. a falling edge of negative pulse with minimum width of t ilih (250ns) on any con?ured port a pins will cause a keyboard interrupt to occur. a keyboard interrupt is recognized by the interrupt ?g keyf in the miscellaneous register (bit 4 of address $17). this ?g is cleared by writing a logic ? to this bit. when the interrupt is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks any further interrupt until the present one is serviced. the keyboard interrupt causes the program counter to vector to memory location $fff0 and $fff1 which contains the starting address of the interrupts service routine. when con?ured, the keyboard interrupt lines remain active in during stop mode. this allows a keyboard interrupt to wake up the mcu when in stop mode. see figure 5-4 for keyboard interrupt circuit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous register $17 por intf1 intf2 keyf r000 ---- r=1 for por; r=0 for reset tpg 41
motorola 5-8 mc68hc05f8 interrupts 5 5.4.1 keyboard control register keye 1 (set) pa0-pa3 are con?ured as keyboard interrupt lines with internal pull-up. 0 (clear) pa0-pa3 are con?ured as standard i/o lines. keyx7, keyx6, keyx5, keyx4 these four bits con?ure their corresponding port a lines. 1 (set) pax is con?ured as a keyboard line with internal pull-up. 0 (clear) pax is con?ured as a standard i/o line. 5.5 programmable timer (timer a) interrupt three timer interrupt ?gs are found in the three most signi?ant bits of the timer status register (tsr) at location $19. all three interrupts will vector to the same address at location $fff6-$fff7. each ?g bit is de?ed as follows: tof - timer over?w flag tof is set during the counter transition of $ffff to $0000. it is cleared by reading the tsr (with tof set) followed by reading the counter least signi?ant byte ($1f). ocf - output compare flag ocf is set when the output compare register matches the counter register. it is cleared by reading the tsr (with ocf set) and then accessing the output compare register least signi?ant byte ($1d). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $34 keye keyx7 keyx6 keyx5 keyx4 0--- 000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status register $19 icf ocf tof uuu- ---- tpg 42
mc68hc05f8 motorola 5-9 interrupts 5 figure 5-4 keyboard interrupt circuit & + & & & & & & keye keyx7 keyx4 keyx5 keyx6 port a ddr bit x select port a data bit x vdd pax 250k w port a bit x data line ddra bit x line to cpu key x is a port a line key is keye for pa0-pa3 and keyx4-keyx7 for pa4-pa7 respectively (a) pull-up circuit for port a lines keyboard interrupt pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 keyboard control register (b) keyboard interrupt circuit tpg 43
motorola 5-10 mc68hc05f8 interrupts 5 icf - input capture flag icf is set when a proper edge has been sensed by the input capture edge detector. it is cleared by an cpu read of the tsr (with icf set) followed by accessing the input capture register least signi?ant byte ($1b). all three timer interrupt ?gs have corresponding enable bits (icie, ocie, and toie) found in the timer control register (tcr) at location $18. reset clears all enable bits preventing an interrupt from occurring. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is speci?d by the contents of $fff6 and $fff7. refer to section 6.1 for detailed description of programmable timer. 5.6 reloadable timer (timer b) interrupt timer b interrupt (tuf) occurs only when the timer b counter rolls over from $0001 to $0000 if the timer b interrupt enable bit (tboie in timer b control & status register $22) is set. the interrupt service routine address is speci?d by the contents of memory location $fff8-$fff9. refer to section 6.2 - reloadable timer b for detailed description. 5.7 spi interrupt an interrupt in the serial peripheral interface (spi) occurs when the spi interrupt ?g in the serial peripheral status register (bit 7 of address $11) is set, provided the interrupt mask bit in the condition code register is cleared and the enable bit in the serial peripheral control register ($10) is enabled. when the interrupt is recognized, the current state of the cpu is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks any further interrupt until the present one is serviced. the spi interrupt causes the program counter to vector to memory location $fff4 and $fff5 which contains the starting address of the interrupts service routine. the spi ?g is cleared by accessing the serial peripheral status register (with spif set) followed by a read or write of the serial peripheral data register, at location $12. refer to section 7 for detailed description of the serial peripheral interface. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $22 tmbe tboie tcsb1 tcsb0 tuf 00-- -000 tpg 44
mc68hc05f8 motorola 5-11 interrupts 5 5.8 manchester coder (mancd) interrupt a manchester coder interrupt occurs when one of the interrupt ?gs in the mancd status register (location $2c) is set, provided the interrupt mask bit in the condition code register is cleared and the enable bit in the mancd control register ($2b) is enabled. when the interrupt is recognized, the current state of the cpu is pushed onto the stack and the interrupt mask bit in the condition code register is set. this masks any further interrupt until the present one is serviced. the mancd interrupt causes the program counter to vector to memory location $fff2 and $fff3 which contains the starting address of the interrupts service routine. software in the mancd interrupt service routine must determine the priority and the cause of the mancd interrupt by examining the interrupt ?gs located in the mancd status register. there are four interrupt ?gs associated with mancd interrupts: ncm - encoder data register empty flag 1 (set) encoder data register is empty. 0 (clear) encoder data register is not empty. this bit is cleared by accessing the mancd status register (with ncm set), followed by writing to the encoder data register. ncc - encoding completion flag 1 (set) encoder is disabled (nce=0) or, nce=1 and transmission of the data in the shift register is completed. 0 (clear) transmission of data in process. this bit is cleared by writing to the encoder data register when nce bit is set. dcf - decoder data register full flag 1 (set) one byte of data received with end pattern veri?d. 0 (clear) decoder data register not full. this bit is cleared when the mancd status register is accessed (with dcf set) followed by a read of the decoder data register, or by clearing the dce bit. ovf - overrun flag 1 (set) an overrun has occurred. 0 (clear) an overrun has not occurred. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $2c ncm ncc dcf ovf - - - - 1100 ---- tpg 45
motorola 5-12 mc68hc05f8 interrupts 5 this bit is cleared when the dce bit is cleared. refer to section 8 for detailed description of the manchester encoder/decoder (mancd). tpg 46
mc68hc05f8 motorola 6-1 timers 6 6 timers 6.1 timer a - programmable timer the timer consists of a 16-bit free-running counter driven by a ?ed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. figure 6-1 shows a block diagram for the programmable timer. because the timer has a 16-bit architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers (high byte and low byte). generally, assessing the low byte of a speci? timer function allows full control of that function. however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. note: the i bit in the condition code register should be set while manipulating both the high and low byte register of a speci? timer function to ensure that an interrupt does not occur. ten 8-bit registers are associated with the programmable timer. timer control register (tcr) $18 timer status register (tsr) $19 input capture register high byte - $1a, low byte - $1b output compare register high byte - $1c, low byte - $1d counter register high byte - $1e, low byte - $1f alternate counter register high byte - $20, low byte - $21 a description of each register is provided in the following paragraphs. 6.1.1 counter timer a counter high byte - $1e, low byte - $1f timer a alternate counter high byte - $20, low byte - $21 tpg 47
motorola 6-2 mc68hc05f8 timers 6 figure 6-1 programmable timer block diagram mc68hc05f8 internal bus output compare register 16 bit free running counter counter alternate register 8 bit buffer input capture register output compare circuit overflow detect crcuit edge detect register ? 4 icie ocie toie iedg olvl icf ocf tof interrupt circuit & d c r q timha internal processor clock timer control register output level register edge input (tcap) output level (tcmp) timer status register reset ? m (m=1, 4, 8, or 16) tcsa0 tcsa1 timer internal clock tpg 48
mc68hc05f8 motorola 6-3 timers 6 the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by two prescalers. the ?st stage programmable prescaler provides a slow timer clock by dividing the internal processor clock either by 1, 4, 8, or 16. the second stage is a ?ed divide by four prescaler. see figure 6-1 and table 6-1 for prescaler values. the counter is incremented during the low portion of the internal bus clock, and the counting can be inhibited by setting the timha bit in the event enable register (bit 7 of address $16). software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $1e & $1f (counter register) or $20 & $21 (counter alternate register). reading only the least signi?ant byte (lsb) of the free-running counter ($1f or $21) receives the count value at the time of the read. if the most signi?ant byte (msb) ($1e or $20) is read ?st, the lsb ($1f or $21) is transferred to a buffer. this buffer value remains ?ed after the ?st msb read, even if the msb is read several times. this buffer is accessed when the lsb ($1f or $21) is read, and thus, completes a read sequence of the complete counter value. reading the timer counter register low byte after reading the timer status register clears the timer over?w ?g (tof), but reading the counter alternate register does not affect tof. therefore, the counter alternate register can be read any time without risk of missing timer over?w interrupts due to a cleared tof. the free-running counter is preset to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. the value in the free-running counter repeats every (262144 ? r tb ) internal bus clock cycles (t cyc ). r tb is the ratio of timer clock to bus clock frequency, and is dependent on the values of tcsa0 and tcsa1 bits. tof is set when the counter over?ws (from $ffff to $0000); this will cause an interrupt if toie in the timer control register is set (bit 5 of address $18). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset system option register $35 - tcsa1 tcsa0 intn1 intn2 - - - -000 0--- table 6-1 timer a clock frequency selection tcsa1 tcsa0 clock frequency of timer a 0 0 e/4 0 1 e/16 1 0 e/32 1 1 e/64 where e = internal bus clock tpg 49
motorola 6-4 mc68hc05f8 timers 6 6.1.2 output compare registers output compare register high byte - $1c, low byte - $1d the 16-bit output compare register is made up of two 8-bit registers. this output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not affected by the timer hardware or reset. if the compare function is not needed, the output compare register can be used as storage locations. the contents of the output compare register are continually compared with the contents of the free-running counter and, if a match is found, the output compare flag (ocf) in the timer status register is set; and the output level (olvl) bit is clocked to an output level register. the output compare register value and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the interrupt enable bit (ocie) is set. (the free-running counter is updated every 4 ? r tb internal bus clock cycles.) after a processor write cycle to the output compare register containing the msb ($1d), the output compare function is inhibited until the lsb ($1d) is also written. the user must write both bytes (locations) if the msb is written ?st. a write made only to the lsb ($1d) will not inhibit the compare function. the processor can write to either byte of an output compare register without affecting the other byte. the minimum time required to update the output compare registers is a function of the program rather than the internal hardware. because the output compare ?g and output compare register are not de?ed at power-on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: 1) write to output compare register high-byte to inhibit further compares; 2) read the timer status register to clear ocf; 3) write to output compare register low-byte to enable the output compare function. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare ?g (ocf) is set or clear. 6.1.3 input capture registers input capture register high byte - $1a, low byte - $1b ?nput capture is a technique whereby an external signal (connected to tcap pin) is used to trigger a read of the free-running counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. the two 8-bit registers that make up the 16-bit input capture register, are read-only, and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a valid transition. the level transition that triggers the counter transfer is de?ed by the tpg 50
mc68hc05f8 motorola 6-5 timers 6 corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is zero or one count of the free-running counter, which is 4xr tb internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture ?g (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture.after a read of the input capture register msb ($1a), the counter transfer is inhibited until the lsb ($1b) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($1b) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 6.1.4 timer control register (tcr) the tcr is a read/write register containing ?e control bits. three bits control interrupts associated with the three ?g bits found in the timer status register (discussed below). the other two bits control: 1) which edge is signi?ant to the input capture edge detector (i.e., negative or positive), and 2) the next value to be clocked to the output level registers in response to a successful output compare. the timer control register and the free-running counter are the only sections of the timer affected by reset. the tcmp pin is forced low during external reset and stays low until a valid compare changes them to high. de?ition of each bit is as follows: icie - input capture interrupt enable 1 (set) input capture interrupt enabled. 0 (clear) input capture interrupt disabled. ocie - output compare interrupt enable 1 (set) output compare interrupt enabled. 0 (clear) output compare interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $18 icie ocie toie 0 0 0 iedg olvl 0000 00u0 tpg 51
motorola 6-6 mc68hc05f8 timers 6 toie - timer over?w interrupt enable 1 (set) timer over?w interrupt enabled. 0 (clear) timer over?w interrupt disabled. iedg - input edge 1 (set) tcap is positive-going edge sensitive. 0 (clear) tcap is negative-going edge sensitive. when iedg is set, a positive-going edge on the tcap pin will trigger a transfer of the free-running counter value to the input capture registers. when clear, a negative-going edge triggers the transfer. olvl - output level voltage latch 1 (set) high output on tcmp pin if counter compare is true. 0 (clear) low output on tcmp pin if counter compare is true. there is a bit in the event enable register which may be used to disable and enable the programmable timer. timha - timer a enable/disable 1 (set) timer inhibit 0 (clear) enable timer (default at reset) 6.1.5 timer a status register (tsr) the timer status register ($19) contains the status bits for the above three interrupt conditions - icf, ocf, tof. accessing the timer status register satis?s the ?st condition required to clear the status bits. the remaining step is to access the register corresponding to the status bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset event enable register $16 timha inte1 inte2 0 0 0 0 0 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $19 icf ocf tof 0 0 0 0 0 uuu0 0000 tpg 52
mc68hc05f8 motorola 6-7 timers 6 icf - input capture flag 1 (set) a valid input capture has occurred. 0 (clear) no input capture has occurred. this bit is set when the selected polarity of edge is detected by the input capture edge detector; an input capture interrupt will be generated, if icie is set, icf is cleared by reading the tsr and then the input capture low register ($1b) ocf - output compare flag 1 (set) a valid output compare has occurred on output compare register. 0 (clear) no output compare has occurred on output compare register. ocf will be set when its output compare register contents match that of the free-running counter; an output compare interrupt will be generated, if ocie is set. ocf is cleared by reading the tsr and then the output compare low register ($1d). tof - timer over?w flag 1 (set) timer over?w has occurred. 0 (clear) no timer over?w has occurred. this bit is set when the free-running counter over?ws from $ffff to $0000; a timer over?w interrupt will occur, if toie (bit 5 in timer control register $18) is set. tof is cleared by reading the tsr and the counter low register ($1f). when using the timer over?w function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer over?w ?g is unintentionally cleared if: 1) the timer status register is read or written when the tof is set, and 2) the lsb of the free-running counter is read, but not for the purpose of servicing the ?g. reading the alternate counter register instead of the counter register will avoid this potential problem. 6.1.6 programmable timer timing diagrams the relationships between the internal clock signals, the counter contents and the status of the ?g bits are shown in the following diagrams. it should be noted that the signals labelled ?nternal (processor clock, timer clocks and reset) are not available to the user. the timing diagrams are for a timer clock frequency of internal bus clock ? 4; tcsa0=tcsa1=0. tpg 53
motorola 6-8 mc68hc05f8 timers 6 figure 6-2 timer state timing diagram for reset figure 6-3 timer state timing diagram for input capture $fffc $fffd $fffe $ffff internal processor clock internal reset t00 t01 t10 t11 counter (16 bit) reset (external or end of por) internal timer clocks notes: reset affects only the counter register and timer control register. internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $f123 $f124 $f125 $f126 $f127 $f125 $???? (see note) input edge internal capture latch input capture register input capture flag if the input edge occurs in the shaded area from one timer state t10 to the other timer state t10 the input capture ?g is set during the next state t11. note: tpg 54
mc68hc05f8 motorola 6-9 timers 6 figure 6-4 timer state timing diagram for output compare figure 6-5 timer state diagram for timer over?w internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $f455 $f456 $f457 $f458 $f459 note 1 note 2 $f457 cpu writes $f457 output compare register compare register output compare flag (ocf) and tcmp note: 1. the cpu write to the compare registers may take place at any time, but a compare only occurs at the timer state t01. thus a 4-cycle difference may exist between the write to the compare register and the actual compare. 2. the output compare ?g is set at the timer state t11 that follows the comparison match ($f547 in this example). latch note 1 internal processor clock t00 t01 t10 t11 counter (16 bit) internal timer clocks $fffe $ffff $0000 $0001 $0002 note: timer overflow flag (tof) the tof bit is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by a read of the timer status register during the internal processor clock high time followed by a read of the counter low register. tpg 55
motorola 6-10 mc68hc05f8 timers 6 6.2 timer b - reloadable timer the reloadable timer is similar to the free-running timer, with the following differences: the 16-bit timer counter is automatically reloaded from the preset timer registers upon under?w occurs. there is no input capture function, i.e. no tcap. there is no output compare function, i.e. no tcmp. the reloadable timer is convenient for generating periodic interrupts without the aid of software. in addition, the timer counter value can be read in a similar way to timer a. 6.2.1 functional description see figure 6-6 for a block diagram of the reloadable timer. the timer b is driven by a clock which is derived from e divided by 4, 8, 16 or 32. in the control register, two bits tcsb0 and tcsb1 are used to select the divider for the prescaler, tboie is an interrupt enable bit, tmeb is a timer b enable bit which will inhibit the driving clock when it is clear. upon reset, the control register is cleared, timer b is disabled, timer b interrupt is inhibited, the free running counter and the preset register are all con?ured to $ffff. the preset register should be written with proper value before enable the timer b. a low to high transition of the tmbe bit loads the timer counter with the content in the preset register and activates the driving clock, then the free running counter starts to count down, when it rolls over from $0001 to $0000 an interrupt is generated with timer b under?w ?g set if the tboie is set, meanwhile a ?oad signal is produced to reload the counter with the content of the preset register, thus interruption will occur periodically. 6.2.2 resolution and maximum period when a 3.579mhz crystal is used, the timer resolution and its maximum period are shown in table 6-2. table 6-2 reloadable timer resolution and maximum period tcsb1 tcsb0 frequency resolution max. period preset $ffff 0 0 e/4 2.25 m s 147ms 0 1 e/8 4.5 m s 294ms 1 0 e/16 9 m s 588ms 1 1 e/32 18 m s 1176ms where e = internal bus clock tpg 56
mc68hc05f8 motorola 6-11 timers 6 6.2.3 timer b counter timer b counter high byte - $25, low byte - $26 timer b alternate counter high byte - $27, low byte - $28 the double-byte, reloadable timer counter can be read from either of two locations, $25 & $26 (timer b counter register) or $27 & $28 (timer b counter alternate register). reading only the least signi?ant byte (lsb) of the free-running counter ($26 or $28) receives the count value at figure 6-6 reloadable timer block diagram mc68hc05f8 internal bus active 16 bit free running counter counter alternate register 8 bit buffer 16 bit timer preset register underflow detect crcuit & internal processor clock timer b control register ? 4/8/16/32 tcsb1 tcsb0 tcsb1 tcsb0 tmbe tboie tuf & logic lo ad timer b interrupt tpg 57
motorola 6-12 mc68hc05f8 timers 6 the time of the read. if the most signi?ant byte (msb) ($25 or $27) is read ?st, the lsb ($26 or $28) is transferred to a buffer. this buffer value remains ?ed after the ?st msb read, even if the msb is read several times. this buffer is accessed when the lsb ($26 or $28) is read, and thus, completes a read sequence of the complete counter value. 6.2.4 timer b preset register timer b preset register high byte - $23, low byte - $24 on the low to high transition of the tmbe bit, the reloadable timer is loaded with the value set in this 16-bit register. 6.2.5 timer b control status register tmbe - timer b enable/disable 1 (set) timer b enabled. 0 (clear) timer b disabled. upon reset, this bit is cleared and the driving clock of timer b is inhibited, a low to high transition of this bit loads the timer b counter with the contents of the preset register and activates the driving clock. tboie - timer b time-out interrupt enable/disable 1 (set) timer b time-out interrupt enabled. 0 (clear) timer b time-out interrupt disabled. when this bit is set, timer b time out interrupt will occur if the time out ?g (tuf) is set; otherwise, time out interrupt is disabled. tcsb1, tcsb0 - timer b clock frequency select these two bits are used to select the frequency of timer b driving clock. see table 6-2. tuf - timer b under?w flag this bit is set when the counter of timer b rolls from $0001 to $0000. it should be cleared by software in the timer b interrupt service routine. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $22 tmbe toie tcsb1 tcsb0 tuf 00-- -000 tpg 58
mc68hc05f8 motorola 6-13 timers 6 6.3 cop watchdog a cop (computer operating properly) watchdog timer is implemented to restore system operation in the event of system lock-up. this timer consists of a counter which is clocked by a 4hz signal; the time-out period is software programmable to approximately 0.5, 1, 2 or 4 seconds (default time out period is 0.5s after a reset). a watchdog reset occurs when the watchdog timer times out, unless the timer is periodically reset by writing to the watchdog timer control status register. 6.3.1 watchdog timer time-out flag a watchdog time-out ?g (wdtof) is provided in the watchdog control status register (wdcsr, $36), to allow the user to distinguish between a normal reset (power-on-reset or external reset) and a watchdog timer reset. this bit is a logic ? if the reset was due to a watchdog time-out and logic ? for a normal reset; and is cleared by reading the wdcsr register. writing a logic ? to this bit has no effect on its value other than resetting the watchdog timer counter. figure 6-7 watchdog timer block diagram watchdog control register wdt1 wdt0 wdtof kwdt wdte mc68hc05f8 internal bus & & & + watchdog timer counter time-out detector time-out value active logic wake-up 4hz clock wdtof reset st opm w aitm tpg 59
motorola 6-14 mc68hc05f8 timers 6 6.3.2 cop system enable and operation a watchdog timer enable (wdte) bit in the wdcsr is used to enable the cop watchdog system. its default value is ? at reset (watchdog disabled). writing a ? to this bit will load the watchdog timer counter with the initial value selected by wdt0 & wdt1 bits and activate the watchdog timer clock. when the watchdog timer counter reaches zero, a watchdog time-out signal is generated to reset the mcu with wdtof set. once the watchdog is enabled, it cannot be disabled by software; writing a ? to the wdte bit has no effect. 6.3.3 disable cop function in stop or wait mode a kill watchdog timer (kwdt) bit is provided in the wdcsr to optionally disable and reset the watchdog timer when the stop or wait instruction is executed. this allows the cpu to go into an extended sleep or wait mode without watchdog timer resets. this feature is not enabled if the kwdt bit is set to ?? the kwdt bit permits a ?top or ?ait instruction to disable the watchdog timer. to do so, kwdt must be written to a logic ? on the ?st write to the wdcsr after a reset. however, this ?st write only enables the ?ill feature. a second write of a logic ? to kwdt must be performed to engage the ?ill feature. after the second write, the execution of a stop or wait instruction will reset the watchdog timer and disable the cop watchdog system. two speci? writes are required for this feature to prevent accidental engagement by a single spurious write. the watchdog counter resumes counting when the mcu exits stop or wait mode. 6.3.4 watchdog timer control status register (wdcsr) wdte - watchdog timer enable/disable 1 (set) watchdog timer enabled. 0 (clear) watchdog timer disabled. the default for the watchdog timer at reset is disabled. once enabled by writing a logic ? to this bit, it cannot be disabled by software. writing a logic ? have no effect to this bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $36 wdte kwdt wdtof wdt1 wdt0 000- --00 tpg 60
mc68hc05f8 motorola 6-15 timers 6 kwdt - kill watchdog timer bit 1 (set) enable watchdog ?ill feature. 0 (clear) disable watchdog ?ill feature. when this watchdog ?ill feature is set by writing a logic ? to this bit immediately after a reset, the watchdog timer will be disabled when the mcu in stop or wait mode. the default for the watchdog timer ?ill feature at reset is disabled. reading this bit will show the value of ?st write after reset or the default value upon reset. wdtof - watchdog timer time-out flag 1 (set) a watchdog timer time-out has occurred. 0 (clear) a watchdog timer time-out has not occurred. this ?g is cleared by writing a logic ? to this bit. writing a logic ? to this bit will reset the watchdog timer counter, and hence avoiding a watchdog time-out. the write does not affect the time-out ?g. wdt1, wdt0 - time-out period select wdt1 wdt0 time-out period min. (s) max. (s) 0 0 0.25 0.5 0 1 0.75 1.0 1 0 1.75 2.0 1 1 3.75 4.0 tpg 61
motorola 6-16 mc68hc05f8 timers 6 this page left blank intentionally tpg 62
mc68hc05f8 motorola 7-1 serial peripheral interface 7 7 serial peripheral interface the serial peripheral interface (spi) is an interface built into the mc68hc05f8 mcu which allows two mc68hc05f8 mcus to be interconnected within a single ?lack box or on the same printed circuit board. in a serial peripheral interface (spi), separate wires (signals) are required for data and clock. in the spi format, the clock is not included in the data stream and must be furnished as a separate signal. an spi system may be con?ured in one containing one master and one slave mcus. figure 7-1 illustrates a normal system con?urations. in this system three basic lines (signals) are required for the serial clock (sck), serial data input (sdi), and serial data output (sdo) lines. 7.1 features full duplex, three-wire synchronous transfer master or slave operation 447.5 khz master bit frequency 1.79mhz (max.) slave bit frequency end of transmission interrupt ?g data collision ?g protection 7.2 signal description the three basic signals (sck, sdo and sdi) are described in the following paragraphs. each signal function is described for both the master and slave mode. figure 7-2 summarizes the spi port timing for data exchange operation. tpg 63
motorola 7-2 mc68hc05f8 serial peripheral interface 7 7.2.1 serial clock (sck) the state of sck between transmissions must be logic ?? the ?st falling edge of sck signals the beginning of a transmission. at this time the msb bit of received data is accepted at the sdi pin and the msb bit of transmitted data is presented at the sdo pin. data is captured at the sdi pin on the rising edge of sck. subsequent falling edges shift the data, and accept the next received data bit at sdi pin, and present the next transmitted data bit at sdo pin. the transmission is ended upon the receipt of the lsb bit. in master mode, the format is identical except that the sck pin is an output and the shift clock now originates internally. the master mode transmission frequency is ?ed at e/4. care should be taken when enabling the spi; additional clock edges may be present when the port is switched from standard i/o to spi. figure 7-1 spi master-slave interconnection figure 7-2 spi port timing 8-bit shift register spi master slave sdo sdo sdi sdi sck sck 8-bit shift register clock generator (447.5khz) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 112ns 112ns sck sdo sdi tpg 64
mc68hc05f8 motorola 7-3 serial peripheral interface 7 7.2.2 serial data output (sdo) data is transmitted in msb ?st format. the state of the sdo pin will always re?ct the value of the ?st bit receive on the previous transmission if there was one. prior to enabling the spi, pd5 can be initialized to determine the beginning state if a standard output since that pin is coupled to the last stage of the serial shift register. on the first falling edge of sck the ?st data bit to be shifted out is presented to the output pin. 7.2.3 serial data input (sdi) the sdi pin becomes an input as soon as the spi pin on the falling edge of sck. valid data must be present at least 112ns before the rising edge of the clock and remain valid for 112ns after the edge. 7.3 general operation a block diagram of the serial peripheral interface (spi) is shown in figure 7-3. in a master con?uration, the master start logic originates the system clock (sck) based on the 447.5khz (or the e/4) clock. this clock is also used internally to control the state controller as well as the 8-bit shift register. as a master device, data is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle, data is applied serially from a slave device via sdi pin to the 8-bit shift register. after the 8-bit shift register is loaded, its data is parallel transferred to the read buffer and then is made available to the internal data bus a cpu read cycle. in a slave con?uration, the slave start logic receives a system clock input (from the master device) at sck pin. thus, the slave is synchronized with the master. data from the master is received serially at the slave sdi and loads the 8-bit shift register. after the 8-bit shift register is loaded, its data is parallel transferred to the read buffer and then is made available to the internal data bus during a cpu read cycle. during a write cycle, data is parallel loaded into the 8-bit shift register from the internal data bus and then shifted out serially to the sdo pin for application to the master device. one point to be noted, the sck pin needs to be externally pulled high with 10k ohms, in order to bias the initial states at logic high. 7.4 spi registers there are three registers associated with the serial parallel interface. they are the serial peripheral control register (spcr, location $10), the serial peripheral status register (spsr, location $11), and the serial peripheral data i/o register (spdr, location $12). each register are described below. tpg 65
motorola 7-4 mc68hc05f8 serial peripheral interface 7 7.4.1 spi control register (spcr) spie - serial peripheral interrupt enable when the serial peripheral interrupt enable bit is high, it allows the occurrence of a processor interrupt and forces the proper vector to be loaded into the program counter if the serial peripheral figure 7-3 spi block diagram address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $10 spie spe mstr 00-0 ---- master start logic slave start logic control bits sck sdo sdi read buffer 8-bit shift register state controller flags (load) (full) write spcr spsr 2 3 8 8 read internal data bus note: sck, mosi, and miso are external pins; where sck - provides system clock when device is con?ured as a master unit. receives system clock when device is con?ured as a slave unit. sdi - provides serial output to slave unit when device is con?ured as a master. receives serial input from master when device is con?ured as a slave unit. sdo - receives serial input from slave unit when device is con?ured as a master. provides serial output to master when device is con?ured as a slave unit. spif e/4 clock 8 tpg 66
mc68hc05f8 motorola 7-5 serial peripheral interface 7 status register bit (spif) is set to a logic one. it does not inhibit the setting of a status bit. the spie bit is cleared by reset. spe - serial peripheral enable when set, this bit enables the serial i/o port and initializes the port d ddr such that pd5 (sdo) is output, pd6 (sdi) is input and pd7 (sck) is input (slave mode only). the port d ddr can be subsequently altered as the application requires and the port d data register (except for pd5) can be manipulated as usual, however these actions could affect the transmitted or received data. when spe is cleared, port d reverts to standard parallel i/o without affecting the port d data register or ddr. spe can be read or written any time, but clearing spe while a transmission is in progress will abort the transmission, reset the bit count and return port d to its normal i/o function. reset clears this bit. mstr - master bit when set, this bit con?ures the spi for master mode. this means that the transmission is initiated by a write to the data register and the sck pin becomes an output providing a synchronous data clock at a ?ed rate of e clock divided by 4. while the device is in master mode, the sdo and sdi pins do not change function. these pins behave exactly as they would in slave mode. reset clears this bit and con?ures the spi for slave operation. mstr may be set at any time regardless of the state of spe. clearing mstr will abort any transmission in progress. 7.4.2 spi status register (spsr) spif - serial peripheral interface flag the serial peripheral data transfer ?g bit noti?s the user that a data transfer between the device and an external device has been completed. with the completion of the data transfer, spif is set, and if spie is set, a serial peripheral interrupt (spi) is generated. during the clock cycle that spif is being set, a copy of the received data byte in the shift register is moved to a buffer. when the data register is read, it is the buffer that is read. the transfer of data is initiated by the master device writing its serial peripheral data register. clearing the spif bit is accomplished by a software sequence of accessing the serial peripheral status register while spif is set and followed by a write to or a read of the serial peripheral data register. while spif is set, all writes to the serial peripheral data register are inhibited until the serial peripheral status register is read. this occurs in the master device. in the slave device, spif can be cleared before the second spif in order to prevent an overrun condition. the spif bit is cleared by reset. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $11 spif dcol 00-- ---- tpg 67
motorola 7-6 mc68hc05f8 serial peripheral interface 7 dcol - data collision this is a read only status bit which indicates that an invalid access to the data register has been made. this can occur any time after the ?st falling edge of sck and before spif is set. a read or write of the data register during this time will result in invalid data being transmitted or received. dcol is cleared by reading the status register with spif set followed by a read or write of the data register. if the last part of the clearing sequence is done after another transmission has been started, dcol will be set again. reset also clears this bit. 7.4.3 serial peripheral data register (spdr) the serial peripheral data i/o register is used to transmit and receive data on the serial bus. only a write to this register will initiate transmission/reception of another byte and this will only occur in the master device. a slave device writing to its data i/o register will not initiate a transmission. at the completion of transmitting a byte of data, the spif status bit is set in both the master and slave devices. a write or read of the serial peripheral data i/o register, after accessing the serial peripheral status register with spif set, will clear spif. during the clock cycle that the spif bit is being set, a copy of the received data byte in the shift register is being moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. during an overrun condition, when the master device has sent several bytes of data and the slave device has not internally responded to clear the ?st spif, only the ?st byte is contained in the receive buffer at any time. the ?st spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. a write to the serial peripheral data i/o register is not buffered and places data directly into the shift register for transmission. the ability to access the serial peripheral data i/o register is limited when a transmission is taking place. it is important to read the discussion de?ing the dcol and spif status bits to understand the limits on using the serial peripheral data i/o register. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $12 tpg 68
mc68hc05f8 motorola 8-1 manchester encoder/decoder 8 8 manchester encoder/decoder the built-in full duplex manchester coder (mancd) performs data format conversion between parallel nrz and serial manchester code. the bit rate is programmable, in four steps between 600 and 4800 baud when a 3.579mhz crystal is used. data are encoded to manchester codes by writing to the encode register before it is output to the encoout pin. the data transfer format is 2 sync bits followed by 8 data bits and a trailing bit. two low level bits are used as a pause between byte transfers. figure 8-3 shows the one byte data transfer. manchester codes enter the mcu, lsb ?st, at the decoin pin to the decode register, gets decoded before processing. the idle state of the decoin pin is a logic high. a schmitt trigger is built in at the decoin input to improve noise immunity. 8.1 features four programmable bit rates buffered encode data register and decode data register encode data register empty ?g and interrupt encoding complete ?g decode data register full ?g and interrupt decode overrun ?g and interrupt bit format error detection bit rate error detection built-in front end schmitt trigger in decoder tpg 69
motorola 8-2 mc68hc05f8 manchester encoder/decoder 8 8.2 general operation figure 8-1 shows a block diagram of the manchester encoder/decoder. logic ?w of the hardware operation of the encoder and decoder are shown in figure 8-2 and figure 8-3 respectively. 8.2.1 encoder the manchester encoder is used to convert data from nrz format to manchester code format; and output onto the encoout pin. figure 8-1 manchester encoder/decoder block diagram mc68hc05f8 internal bus nce nie cie dce die br1 br0 ncm ncc dcf ovf prescaler divider encode register encode shift register decode register decode shift register manchester encoder logic encode control decode control manchester decoder logic interrupt generator mancd status register mancd control register encoout decoin internal bus clock int tpg 70
mc68hc05f8 motorola 8-3 manchester encoder/decoder 8 8.2.1.1 idle state of encoder upon reset the encoder enable bit (nce) is cleared, encoout pin is at high impedance, internal encoding clock is inhibited, and the encoder is in the idle state. the encode data register empty ?g (ncm) and the encoding completion ?g (ncc) in the status register are both set. 8.2.1.2 initialization of encoder the encoder is initialized by con?uring the bit rate control bits (br0, bs1) and setting nce=1 to place the encoder in the standby state. the encoding process is initiated by writing to the encoder data register, which is then transferred to the encode data shift register ready for encoding. after 2 delay bits (encoout pin is low) and 2 sync bits, the encoded data is shifted out to the encoout pin, lsb ?st. see figure 8-3 for a graphical representation. 8.2.1.3 encode data register empty flag (ncm) and encode interrupt after the last data bit in the encode data shift register is encoded and output to encoout, a trailing bit followed by two pause bits are generated to conclude a one byte transmission. after this, if the encode data register is not empty, the encoding process is repeated. when data from the encode data register is transferred to the encode data shift register, the encoder data register empty ?g (ncm) is set, causing an interrupt to be generated if the encode interrupt is enabled (i.e. nie = 1). the next byte of data to be encoded can be written in to the encoder data register in an interrupt service routine. the ncm bit is automatically cleared by writing to the encode data register after accessing the mancd status register. 8.2.1.4 end pattern generation and next data byte encoding the end pattern of one byte sequence is generated automatically after the last bit. this pattern consists of a trailing bit and two pause bits. after this, if the encode data register is empty, encoout is set to high impedance, and the encoder returns to the standby state. the encoding complete ?g (ncc) will be set, and an interrupt is generated if the encoding complete interrupt enable bit (cie) is set. if the encode data register is not empty, the next encoding is started. 8.2.1.5 disable encoder the encoder is disabled by setting nce=0; causing the encoout pin to be tri-stated. if the nce bit is cleared while an encoding is in progress (indicated by ncc=0), the encoder will complete encoding of the current byte, plus the end patterns, before going into idle. tpg 71
motorola 8-4 mc68hc05f8 manchester encoder/decoder 8 figure 8-2 logic flow of encoder hardware operation idle nce=1? write to encode data register? encoout hi z ? low level (sync with internal transmit clock) standby 2 bits - time delay move data from encode register to encode shift register ncf 0 ? 1 and generate int if nie=1 generate 2 sync bits encode data in the encode register and output generate trailing bit generate 2 bits pause nce=0? encode register empty? ncc 0 ? 1 generate int if cie=1 encoout hi z n y n y n n y y (ncm=1?) nce=0, nie=0, ncm=1, ncc=1 encoout pin hi z tpg 72
mc68hc05f8 motorola 8-5 manchester encoder/decoder 8 8.2.2 decoder the manchester decoder is used to convert incoming manchester codes on the decoin pin to nrz data format for processing. upon reset the decoder is disabled, decoder enable bit dce=0. to initiate the decoding process, the bit rate is ?st con?ured. setting dce activates the internal decoding clock, the decoder enters the start state and the decoin pin begins to be sampled. after a low state is con?med, the receiver starts to hunt for the 2 bits sync pattern. if it is detected, the decoding procedure starts, the decode logic converts the data bits from manchester code format to nrz format and shifts the result to the decode shift register bit by bit. after all 8 bits have been received and converted to one data byte, the end pattern of a trailing bit plus two bit pause is veri?d. if the pattern followed is correct, the decode ?g is set and an interrupt is generated, otherwise the decoder is reset and returns to the start state. 8.2.2.1 decoder overrun after one byte of data is received and end pattern veri?d, the decode output ?g (dcf) is checked ?st, if it is zero (indicating the decode register is empty), one byte of data which has been received is loaded to the decode register and interrupt is generated with the decode output ?g set (dcf=1), otherwise the receive overrun ?g is set and an interrupt is generated. figure 8-3 encoder timing diagram a sequence of one byte data 8 bits data 12345678 encoout d0 d1 d2 d3 d4 d5 d6 d7 00111010 high z high z 1st syn bit 2nd syn bit 2 bits sync 2 bits delay 2 bits pause t 1 bit time nce (encode enable) trailing bit encoder out tpg 73
motorola 8-6 mc68hc05f8 manchester encoder/decoder 8 8.2.2.2 data bit format error detection during decoding, a bit format error detection is performed. if 00 or 11 appears at a time interval in which one bit of data is expected, which means that bit format error occurs, then the decoder is reset and returns to the start state. 8.2.2.3 bit rate error detection during decoding, the input data is sampled by an internal clock, of which the frequency is 8 times of the selected bit rate. if the bit rate of the input data varies exceeding 10% with reference to the nominal value (see bit rate selection table), a bit rate error occurs and the data which is being received is discarded. in this case the decoder is initialized and returns to the start state. 8.3 manchester encoder/decoder registers 8.3.1 mancd control register nce - encoder enable bit 1 (set) enable the encoder. a transition from 0 to 1 of this bit initiates transmission sequence of one byte data, including 2 proceeding idle bits and 2 ending pause bits. 0 (clear) disable the encoder. when this bit is cleared, the encoder (except the control bits) is reset and put in idle state. if the nce bit is cleared while an encoding is in progress (indicated by ncc=0), the encoder will complete encoding of the current byte, plus the end patterns, before going idle. clearing and setting the nce bit during encoding of a byte has no effect on the encoder operation. normally, after the last byte of data is written to the encode data register, the ncm bit will generate an interrupt (if nie=1), indicating that data have been transferred to the encode data shift register. the user should then clear the nce bit to put the encoder in the idle state. nie - encoder interrupt enable bit 1 (set) enable the encoder interrupt. if this bit is set, interrupt is generated when the ncm ?g is set. 0 (clear) disable the encoder interrupt. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $2b nce nie cie dce die br1 br0 0000 0-00 tpg 74
mc68hc05f8 motorola 8-7 manchester encoder/decoder 8 figure 8-4 logic flow of decoder hardware operation reset decoder enabled ? decdain low ? dcf set ? (dce=1) 2 sync bit received ? d0 received with detect correct end pattern ? load decode register with received data, set dcf and generate int if die set set overrun ?g generate int if die set initialize decoder correct format ? d1 received with correct format ? d7 received with correct format ? n y n y y y y y y n y n n n n n tpg 75
motorola 8-8 mc68hc05f8 manchester encoder/decoder 8 cie - encoding complete interrupt enable bit 1 (set) enable encoding complete interrupt. if this bit is set, interrupt is generated when the ncc ?g is set. 0 (clear) disable the encoding complete interrupt. dce - decoder enable 1 (set) enable the decoder. 0 (clear) disable the decoder. when this bit is cleared, the decoder is reset, receive and decode function is disabled. die - decode interrupt enable 1 (set) enable the decoder interrupt. if this bit is set, interrupt is generated when the dcf or ovf ?g is set. 0 (clear) disable the decoder interrupt. br1 & br0 - bit rate select these two bits are used to select the transfer bit rate. 8.3.2 mancd status register ncm - encoder data register empty flag the encoder data register empty ?g is set to indicate the contents of the encoder data register have been transferred to the encode data shift register. if the ncm bit is clear, it indicates that the transfer has not yet occurred and a write to the encode data register will overwrite the previous value. this bit is cleared by accessing the mancd status register (with ncm set), followed by writing to the encode data register. reset sets the ncm bit. br1 br0 bit cycle bit rate (3.579mhz crystal) 0 0 1/8 (e/372) 601 0 1 1/4 (e/372) 1203 1 0 1/2 (e/372) 2405 1 1 e/372 4810 ?it refers to bit unit in nrz format, i.e. one bit is twice the bit unit in manchester format. e = internal bus clock address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $2c ncm ncc dcf ovf 1100 ---- tpg 76
mc68hc05f8 motorola 8-9 manchester encoder/decoder 8 ncc - encoding completion flag this bit is set to indicate that no data transmitting or encoding is in progress. it is set when one of the following cases occurs: 1) the encoder is disabled, i.e. nce=0, transmission of the data in the encode data shift register is completed. 2) the encoder is enabled, nce=1, the encode data register is empty (ncm=1) and transmission of the data in the encode data shift register is completed. writing to the encoder data register when the nce bit is set clears this ?g. reset or clearing the nce bit sets this ncc bit. dcf - decoder data register full flag this bit is set when one byte of data is received with end pattern veri?d, and an interrupt is generated if the decoder interrupt is enabled (die=1). this ?g is cleared when the status register is accessed (with dcf set) followed by a read of the decode data register, or by clearing the dce bit. ovf - overrun flag when an overrun occurs, this ?g is set, and an interrupt is generated if the decode interrupt is enabled. clearing the dce bit will reset the decoder and thus clearing this ?g. see section 8.2.2.1 for de?ition of an overrun condition. 8.3.3 encode data register ($2d) this is a write only register. data written to this register will be encoded to manchester format and then transmitted out to the encoout pin in sequential format. 8.3.4 decode data register ($2e) the is a read only register. data in manchester format entering the decoin pin will be decoded and the result placed in this register. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $2d address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $2e tpg 77
motorola 8-10 mc68hc05f8 manchester encoder/decoder 8 this page left blank intentionally tpg 78
mc68hc05f8 motorola 9-1 dtmf/melody generator 9 9 dtmf/melody generator the dtmf/melody generator (dmg) is a multi-function tone generator built into the mc68hc05f8 mcu, supporting dtmf dialling, melody-on-hold, and paci?r tone functions. the associated output pins are toneout and tonex. 9.1 features 4 row and 4 column frequencies for dtmf dialling 24 row and 24 column frequencies for dual tone melody 28 frequencies for paci?r tone to acknowledge button pressed for pulse dialling power saving mechanism for no tone condition 3.579mhz ? 2 operation 6-bit d/a converter and 28 time steps for sine wave generation sine wave or square wave selectable output for melody or dtmf single or dual tone capability for melody or dtmf 9.2 general operation in figure 9-1, the dmg consists of a row tone and a column tone generation path. the tone frequency of each path is controlled by their respective frequency control registers; row frequency control register (fcr) and column frequency control register (fcc). at the toneout output, single/dual sine/square wave tones of dtmf and melody frequencies are possible, whereas at the tonex output, only single square wave tones are possible. to generate a sine wave tone with programmable frequency in a path, the internal clock (i.e. the 3.58mhz ? 2) is ?st divided by a frequency divider, whose value is set by the frequency control register (fcr or fcc). the output of the divider is a periodic pulse train whose frequency is the tpg 79
motorola 9-2 mc68hc05f8 dtmf/melody generator 9 sampling rate of the desired ?taircase sine wave? this pulse train then clocks a divide-by-28 binary counter (pla scanner) whose 28 decoded outputs sequentially scan 28 memory locations of a 28x6 sine wave generator (pla) in 28 time steps (m). the 6 resulting digital sine wave bits are then fed separately to a 6-bit resistor ladder to produce a current signal. the method for generating a square wave tone in a path is similar to that of a sine wave tone except that only the most signi?ant bit of a sine wave pla is fed to the 6-bit resistor ladder (the other 5 bits are masked by the sine/square wave select) to produce a current signal. the resulting square wave tone has exactly the same frequency and phase as a sine wave tone for the same frequency control register value. after obtaining the current signals from the row and column paths, the row current signal is ?st attenuated by 2db, and is then summed with the column current signal, and is ?ally fed to an active 7khz low pass ?ter to reduce harmonic distortion. the resulting dtmf or melody signal is output to the toneout pin, which is normally buffered to drive a buzzer. the generator provides not only dtmf and melody but also a square wave paci?r tone (tone). this signal is also extracted from the most signi?ant bit of the sine wave pla of the row path, but is not subjected to the ?ter. the tonex signal is output to the tonex pin, which is normally connected to a loudspeaker. figure 9-1 dtmf/melody generator block diagram row frequency divider pla scanner data validator row frequency control register column frequency control register column frequency divider tger tgec ms1 ms0 sinewave pla 28 x 6-bits pla scanner sinewave pla 28 x 6-bits sine/square wave select sine/square wave select mux 6-bit resistor ladder 6-bit resistor ladder high group pre-emphasis + + 3.58mhz ? 2 tonex toneout current summer + active low-pass ?ter msb lsb tone control register bits 4 & 5 tone control register bits 6 & 7 5 6 5 5 6 6 tpg 80
mc68hc05f8 motorola 9-3 dtmf/melody generator 9 9.3 dmg registers the dmg has three registers, row frequency control register and column frequency control register, for row and column frequencies selection respectively; and tone control register for tone output control and mode selection. 9.3.1 row frequency control register (fcr) column frequency control register (fcc) fcr0-4 and fcc0-4 control the frequencies of the tone signals on the row and the column paths respectively. the bit description for dtmf and melody tone generation are shown in table 9-1 and table 9-2 respectively. note: the legal values in the fcr are illegal to the fcc, and vice versa. an illegal value to these registers will produce a tri-state at the toneout output pin, and a logic high at the tonex output pin. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset row frequency control $13 fcr4 fcr3 fcr2 fcr1 fcr0 000u uuuu address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset column frequency control $14 fcc4 fcc3 fcc2 fcc1 fcc0 000u uuuu table 9-1 bit description for dtmf generation fcr fcc tone standard frequency (hz) tone output frequency (hz) frequency deviation (%) $00 see note f r1 697 694.8 0.32 $01 f r2 770 770.1 ?.02 $02 f r3 852 854.2 ?.03 $03 f r4 941 940.0 0.11 see note $10 f c1 1209 1206.0 0.244 $11 f c2 1336 1331.7 0.324 $12 f c3 1477 1486.5 ?.645 $13 f c4 1633 1639.0 ?.367 tpg 81
motorola 9-4 mc68hc05f8 dtmf/melody generator 9 9.3.2 tone control register (tncr) this register controls the internal con?uration and tone output timing of the dtmf/melody generator. ms1, ms0 - mode select these bits control the operating mode of the dtmf/melody generator. these are sine wave, square wave, tonex, and square wave+tonex modes. table 9-3 shows the bit con?urations. table 9-2 bit description for melody generation fcr/fcc tone standard frequency (hz) tone output frequency (hz) frequency deviation (%) $04 d#5 622.3 620.6 0.28 $05 e5 659.3 659.0 0.05 $06 f5 698.5 694.8 0.53 $07 f#5 740.0 743.3 ?.44 $08 g5 784.0 779.5 0.57 $09 g#5 830.6 830.1 0.06 $0a a5 880.6 875.6 0.50 $0b a#5 932.3 926.4 0.64 $0c b5 987.8 983.4 0.45 $0d c6 1046.5 1047.9 ?.13 $0e c#6 1108.7 1102.1 0.60 $0f d6 1174.7 1183.7 ?.77 $14 d#6 1224.5 1253.3 ?.71 $15 e6 1318.5 1331.7 ?.00 $16 f6 1396.9 1389.6 0.52 $17 f#6 1480.0 1486.5 ?.44 $18 g6 1568.0 1559.0 0.57 $19 g#6 1661.2 1682.1 ?.26 $1a a6 1760.0 1775.6 ?.89 $1b a#6 1864.7 1880.0 ?.82 $1c b6 1975.5 1997.5 ?.11 $1d c7 2093.0 2062.0 1.49 $1e c#7 2217.5 2204.2 0.60 $1f d7 2349.3 2367.4 ?.771 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $15 ms1 ms0 tger tgec 0000 0000 tpg 82
mc68hc05f8 motorola 9-5 dtmf/melody generator 9 when one mode is selected, the pin associated with that mode will be activated, but the other pin will remain at its idle state. the idle state for toneout output pin is a tri-state, and tonex output pin is a logic high. the ?al state of an active pin is dependent on the values of tger, tgec (see table 9-4), fcr and fcc bits (when illegal values is input). when both ms1 and ms0 are set, the generator can generate both single tone melody at the column path and tonex at the row path simultaneously. tger, tgec - tone generation enable for row and column paths when both bits are held low, the dmg is disabled by forcing the two frequency counters and the two pla scanning counters to their reset states. the toneout output is set to tri-state, the tonex output is set to logic low, and the active ?ter is turned off by shutting down all related current sources to prevent dc power dissipation. when a tge bit for a path is held high (provided that the value in the frequency control register for that path is legal, and the mode chosen is not tonex mode) the generator is enabled. all the counters associated with that path are then run from their reset states, and the active ?ter is turned on to allow generated tone of that path to be output. in dtmf dialling, the row and column tone values are ?st entered to the fcr and fcc registers, and then the tger and tgec bits are set or reset simultaneously to achieve dual tone multiple frequency. similarly, in melody generation, one path is chosen as the high part, and the other, the low part. the tger and tgec bits are then set and reset according to the rhythm required by the musical tune. of course, one can exhibits only single tone melody by disabling either tger or tgec permanently. the dtmf column and row frequency tones can also be output separately for testing by enabling just the one path. table 9-3 dmg operating modes ms1 ms0 mode toneout output tonex output 0 0 sine wave dtmf/melody high 0 1 square wave melody high 1 0 tonex tri-state tonex 1 1 square wave+tonex monotonic melody tonex table 9-4 effect of tone generation enable on dmg tger tgec row path column path filter tone 0 0 off off off silent 0 1 off active active single 1 0 active off active* single 1 1 active active active dual* * in tonex mode, the ?ter is off and only single tone can be generated. tpg 83
motorola 9-6 mc68hc05f8 dtmf/melody generator 9 note: the reset state of a frequency counter de?es the time=0 state of a time step, whereas the pla scanning counters at its reset state scanning the memory location contained the dc value of staircase sine wave. 9.4 programming the dmg the recommended operating procedures for the dmg are described in the below paragraphs. since the toneout pin is an open-collector output, an external pull-up resistor of 1k to 10k w is required (see section 13 - electrical characteristics). 9.4.1 dtmf dialling to operate dtmf dialling, the sine wave mode selected. the required dual-tone (digit) are selected through the fcr and fcc registers, and are thus output to toneout pin by setting both tger and tgec bits simultaneously for a period of 80ms. after generating a dual-tone, an inter-digit delay, which is produced by tri-stating the toneout output, of another 80ms before the next dual-tone (digit) is output. this can be achieved by clearing both the tger and tgec bits simultaneously, or by writing an illegal value to fcr or fcc registers. 9.4.2 melody generation for melody generation, either sine wave or square wave mode can be selected for full programmability. the sine wave has a ?te like sound, while the square wave possesses much richer harmonics. the required tones are selected through the fcr and fcc registers. the selected tone is generated when the corresponding tger or tgec bit is set. 9.4.3 tonex generation to operate tonex generation, the tonex mode is selected. the required tone is selected through the fcr register. the timing of the tone can be controlled by the tger bit. 9.4.4 melody+tonex generation to operate melody+tonex generation, the tonex+melody mode is selected. the frequencies of the melody tone and tonex are selected through the fcr and fcc registers respectively, whereas the timings of the melody and tonex are controlled separately by tger and tgec respectively. tpg 84
mc68hc05f8 motorola 10-1 cpu core and instruction set 10 10 cpu core and instruction set this section provides a description of the cpu core registers, the instruction set and the addressing modes of the mc68hc05f8. 10.1 registers the mcu contains ?e registers, as shown in the programming model of figure 10-1. the interrupt stacking order is shown in figure 10-2. 10.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. figure 10-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c tpg 85
motorola 10-2 mc68hc05f8 cpu core and instruction set 10 10.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 10.1.3 program counter (pc) the program counter is a 16-bit register, which contains the address of the next byte to be fetched. 10.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. these ten bits are appended to the six least signi?ant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses ?e locations. 10.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ?th bit indicates whether interrupts are masked. these bits can be individually tested by a program, and speci? actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. figure 10-2 stacking order condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return tpg 86
mc68hc05f8 motorola 10-3 cpu core and instruction set 10 interrupt (i) when this bit is set, all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 10.2 instruction set the mcu has a set of 62 basic instructions. they can be grouped into ?e different types as follows: register/memory read/modify/write branch bit manipulation control the following paragraphs brie? explain each type. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 10-1. tpg 87
motorola 10-4 mc68hc05f8 cpu core and instruction set 10 10.2.1 register/memory instructions most of these instructions use two operands. the ?st operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to table 10-2 for a complete list of register/memory instructions. 10.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to table 10-3. 10.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?st 256 bytes of the memory space (page 0). all port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the state of any bit within these locations. the bit set, bit clear, bit test and branch functions are all implemented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 10-4. 10.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?d value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. refer to table 10-5 for a complete list of read/modify/write instructions. 10.2.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to table 10-6 for a complete list of control instructions. 10.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 10-7), and an opcode map for the instruction set of the m68hc05 mcu family (see table 10-8). tpg 88
mc68hc05f8 motorola 10-5 cpu core and instruction set 10 table 10-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 10-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7 tpg 89
motorola 10-6 mc68hc05f8 cpu core and instruction set 10 table 10-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 10-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0?) 2? 3 5 branch if bit n is clear brclr n (n=0?) 01+2? 3 5 set bit n bset n (n=0?) 10+2? 2 5 clear bit n bclr n (n=0?) 11+2? 2 5 tpg 90
mc68hc05f8 motorola 10-7 cpu core and instruction set 10 table 10-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (twos complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 10-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg 91
motorola 10-8 mc68hc05f8 cpu core and instruction set 10 table 10-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc add and asl asr bcc bclr bcs beq bhcc bhcs bhi bhs bih bil bit blo bls bmc bmi bms bne bpl bra brn brclr brset bset bsr clc 0 cli 0 clr 01 cmp condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 92
mc68hc05f8 motorola 10-9 cpu core and instruction set 10 com 1 cpx dec eor inc jmp jsr lda ldx lsl lsr 0 mul 00 neg nop ora rol ror rsp rti ????? rts sbc sec 1 sei 1 sta stop 0 stx sub swi 1 tax tst txa wait 0 table 10-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 93
motorola 10-10 mc68hc05f8 cpu core and instruction set 10 table 10-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3 btb 2 bsc 2 rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg 94
mc68hc05f8 motorola 10-11 cpu core and instruction set 10 10.3 addressing modes ten different addressing modes provide programmers with the ?xibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?ffective address (ea) is used in describing the various addressing modes. the effective address is de?ed as the address from which the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?ontents of the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (program counter). an arrow indicates ?s replaced by and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m68hc05 applications guide . 10.3.1 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 10.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 10.3.3 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) tpg 95
motorola 10-12 mc68hc05f8 cpu core and instruction set 10 10.3.4 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 10.3.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the ?st 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 10.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 10.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg 96
mc68hc05f8 motorola 10-13 cpu core and instruction set 10 10.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from ?26 to +129 from the opcode address. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 10.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode speci?s the address of the byte in which the speci?d bit is to be set or cleared. any read/write bit in the ?st 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 10.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte (ea2) is added to the pc if the speci?d bit is set or cleared in the speci?d memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the ?st 256 locations of memory. the span of branch is from ?25 to +130 from the opcode address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3 tpg 97
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mc68hc05f8 motorola 11-1 low power modes 11 11 low power modes the stop and wait instructions have different effects on the timers, serial peripheral interface (spi), and dtmf/melody generator (dmg). these are discussed in the following paragraphs. 11.1 stop mode when the processor executes the stop instruction, the internal clock is turned off. this halts all internal cpu processing, including the operation of the programmable timer, spi and dmg. the i bit in the condition code register is cleared to enable external interrupts (inte1, inte2 and keye bits are unaltered). all registers and memory remain unaltered, and all input/output lines remain unchanged. the mcu is exited from stop mode by an interrupt on either irq1 or irq2 , or any keyboard interrupts, or any resets (logic low on reset pin or a power-on reset). on exit from stop mode, the program counter is loaded with the corresponding interrupt vector (see table 5-1). the effects of the stop mode on each of the mcu peripheral systems are described separately. 11.1.1 timer a during stop mode when stop mode is entered, the timer a (programmable timer) counter stops counting (the internal processor clock is stopped) and remains at that particular count value until the stop mode is exited. if the exit was caused by reset, the counter is forced to $fffc. if the stop mode is exited by an interrupt (irq1 , irq2 , or keyboard interrupt), the counter resumes counting from the value when it entered the stop mode. another feature of the programmable timer in the stop mode is, that if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuitry is armed. this action does not set any timer ?gs or ?ake up the mcu, but when the mcu does ?ake up there will be an active input capture ?g (and data) from that ?st valid edge which occurred during the stop mode. notice that an exit by a reset will reset the entire mcu and thus, this function on the tcap will not happen. tpg 99
motorola 11-2 mc68hc05f8 low power modes 11 11.1.2 timer b during stop mode when stop mode is entered, the timer b (reloadable timer) counter stops counting (the internal processor clock is stopped) and remains at that particular count value until the stop mode is exited. if the exit was caused by reset, the reloadable timer is disabled. if the stop mode is exited by an interrupt (irq1 , irq2 , or keyboard interrupt), the counter resumes counting from the value when it entered the stop mode. 11.1.3 spi during stop mode when the stop mode is entered, the baud rate generator driving the spi shuts down. this stops all master mode spi operations, thus the master spi is unable to transmit or receive any data. if the stop instruction is executed during an spi transfer, that transfer is halted until the mcu exits the stop mode by an interrupt (irq1 , irq2 , or keyboard interrupt). if the stop mode is exited by a reset, the appropriate control/status bits are cleared and the spi is disabled. if the device is in the slave mode when the stop instruction is executed, the slave spi will still operate. it can still accept data, clock information, and transmit data back to a master device, but no ?gs are set at the end of the transmission until the stop mode is exited by an interrupt. the user should be careful when using the spi as slave during the stop mode because data protection features are not active (e.g. write collision). it should also be noted that when the mcu is in the stop mode, the enabled output drivers (tcmp, sdo, sdi, and sck ports) remain active, and any sourcing currents from these outputs will be part of the total supply current required by the device. 11.1.4 dmg during stop mode when the stop mode is entered, all counters which generate the timings for the dtmf and melody, and all current sources of the active ?ter will be shut down. the toneout pin of the dmg will be tri-stated and the tonex pin will be at logic high. all dmg operations are halted. 11.1.5 cop during stop mode if the cop system is enabled and the ?ill watchdog timer feature is not activated, the watchdog timer will continue to run in stop mode, and eventually time-out, causing a reset to the mcu. if the cop system is enabled and the ?ill watchdog timer is activated, a stop instruction will reset the watchdog timer and disable the cop system. if the wdte bit is set, when the mcu exits stop mode (by an interrupt), the cop system is automatically enabled and the watchdog timer counter is loaded with the initial value. the cop system remains inactive if wdte bit is cleared. tpg 100
mc68hc05f8 motorola 11-3 low power modes 11 11.2 wait mode when the mcu enters the wait mode, the cpu clock is halted. all cpu activities and the dtmf/melody generation are halted, as in stop mode; however, the timers (a and b) and spi system remain active. an interrupt from the timer, keyboard, spi, or irq1 /irq2 causes the processor to exit the wait mode. a reset will also take the mcu out of wait mode. the operation of the cop system in wait mode is as for stop mode. the wait mode power consumption depends on how many systems are active. the power consumption will be the least when the spi and timer are disabled. if a non-reset exit from the wait mode is performed (e.g. timer over?w interrupt exit), the state of the remaining systems will be unchanged. if a reset exit from the wait mode is performed, all the systems revert to the disabled reset state. tpg 101
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mc68hc05f8 motorola 12-1 operating modes 12 12 operating modes the mc68hc05f8/ mc68hc705f8 mcu has two modes of operation, the user mode and the self-check/ bootstrap mode. figure 12-1 shows the ?wchart of entry to these two modes, and table 12-1 shows operating mode selection. figure 12-1 flowchart of mode entering tcap = v dd ? reset irq1 self-check/ mode user mode 5v 9v ? n y y (normal mode) bootstrap note: self-check for mc68hc05f8 bootstrap mode for mc68hc705f8 tpg 103
motorola 12-2 mc68hc05f8 operating modes 12 12.1 user mode (normal operation) the normal operating mode of the mc68hc05f8/ mc68hc705f8 is the user mode. the user mode is entered if the reset line is brought low, and the irq1 pin is within its normal operating range (v ss to v dd ), the rising edge of the reset will cause the mcu to enter the user mode. 12.2 self-check mode the self-check mode is available on the mc68hc05f8 only, and is for the user to check device functions with an on-chip self-check program masked at location $fe00 to $fedf under minimum hardware support. the self-check circuit is shown in figure 12-3. figure 12-2 is the criteria to enter self-check mode, where tcaps condition is latched within ?st two clock cycles after the rising edge of the reset. tcap can then be used for other purposes. after entering the self-check mode, cpu branches to the self-check program and carries out the self-check. self-check is a repetitive test, i.e. if all parts are checked to be good, the cpu will repeat the self-check again. therefore, the leds attached to port a will be ?shing if the device is good; else the combination of leds on-off pattern will indicate which part of the device is suspected to be bad. table 12-2 lists the leds on-off patterns and their corresponding indications. table 12-1 mode selection reset irq1 tcap mode v ss to v dd v ss to v dd user +9v rising edge* v dd self-check/ bootstrap * minimum hold time should be 2 clock cycles, after that it can be used as a normal irq1 function pin. figure 12-2 self-check mode timing 5v 5v 9v tcap irq1 reset +5v +5v +9v tpg 104
mc68hc05f8 motorola 12-3 operating modes 12 figure 12-3 self-test circuit osc1 osc2 mc68hc05f8 10m 22p 3.58mhz +5v 390 390 reset irqa 22p +5v vss 390 390 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa4 pa1 pa5 pa2 pa6 pa3 pa7 +9v pg0 pg1 1 m 100k +5v + reset decoin encoout tcap +5v irqb vdd vpp 4k7 4k7 10k 10k 2n4400 tpg 105
motorola 12-4 mc68hc05f8 operating modes 12 12.3 bootstrap mode the bootstrap mode is available on the mc68hc705f8 only, and it is a mean of self-programming its eprom with minimal circuitry. it is entered on the rising edge of reset if irq1 pin is at 1.8v dd and tcap is at logic one. reset must be held low for 4064 cycles after por (power-on reset) or for a time t rl for any other reset. table 12-3 shows the options that are available once bootstrap mode is entered. the execution result is indicated by two leds. the eprom programming circuit for bootstrap mode is shown in figure 12-5. 12.3.1 eprom program control register eprom programming is controlled by the program control register at location $3f. table 12-2 self-check report pa3 pa2 pa1 pa0 remarks 1 1 1 1 faulty part, port a bad 1 1 1 0 bad i/o 1 1 0 1 bad ram 1 1 0 0 bad rom 1 0 1 1 bad timer a 1 0 1 0 bad timer b 1 0 0 1 bad spi 1 0 0 0 bad mancd 0 1 1 1 bad interrupts flashing good device all others bad device, port a, etc. 1=led off; 0=led on. table 12-3 bootstrap mode options pb0 remarks 0 program & verify 1 verify address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $3f 0 0 0 0 0 0 lat epgm 0000 0000 tpg 106
mc68hc05f8 motorola 12-5 operating modes 12 lat - latch eprom data and address 1 (set) eprom address and data buses con?ured for programming. 0 (clear) eprom address and data buses con?ured for normal reads. lat causes address and data buses to be latched when a write to eprom is carried out. the eprom cannot be read if lat=1. this bit should not be set unless a programming voltage is applied to the vpp pin. epgm - eprom programming mode enable 1 (set) programming power connected to the eprom array. 0 (clear) programming power disconnected from the eprom array. lat and epmg cannot be set on the same write operation. epmg can only be set if lat is set. epmg is automatically cleared when lat is cleared. 12.3.2 eprom programming sequence in the bootstrap, the user program contained in an external eprom is copied into the internal eprom of the mc68hc705f8 device (see figure 12-5). the mc68hc705f8 device is inserted into the programming circuit as shown in figure 12-5. programming routine is selected via mode switch s1, and +5v and vpp power is applied to the programming circuitry. the mcu is removed from the reset state and placed in the run mode of operation via switch s4, and mcu control is transferred to the bootstrap rom. the selected programming routine is then executed. programming sequence of events are as follows: 1) place switch s4 to reset position (switch close). 2) select programming routine via switches s1. 3) apply +5 v and vpp power to programming circuitry. 4) place switch s4 to run position (switch open). 5) programming routine is executed. 6) place switch s4 to reset position. 7) remove vpp and +5 v power, or select and run new routine. once the bootstrap mode is entered, mode switch setting is scanned to establish the routine to be executed. the routines are: program and verify eprom verify eprom contents note: when programming the window part mc68hc705f8, the window should be covered up to prevent erratic device behaviour. tpg 107
motorola 12-6 mc68hc05f8 operating modes 12 12.3.3 program and verify eprom in the program and verify eprom routine, the contents of the external eprom are copied into the eprom areas of the mc68hc705f8 device. there is a direct correspondence of addresses between the two devices. non-eprom addresses are ignored so data contained in those areas are not accessed. unprogrammed eprom address locations should contain $ff to speed up the programming operation. during the programming routine the program/verify led is illuminated. at the end of the programming routine, the led is turned off, and the veri?ation routine is entered. if the contents of the eprom and external eprom exactly match, then the veri?d led is illuminated. the veri?ation routine stops if a discrepancy has been detected. figure 12-4 eprom programming sequence start write additional byte? vpp on lat=1 write eprom byte wait 2ms epmg=1 epmg=8 wait 1ms vpp off end n y tpg 108
mc68hc05f8 motorola 12-7 operating modes 12 12.3.4 verify eprom contents the verify eprom contents routine is normally entered automatically after the eprom is programmed. direct entry of this mode will cause the eprom contents to be compared to external memory contents residing at the same address locations. during execution of the veri?ation routine, the program/verify led is illuminated. upon completion of the veri?ation routine (every location veri?d) the program/verify led is turned off and the veri?d led is turned on. if the program/verify led does not illuminate, a discrepancy has been detected and the error address location will be placed on the external memory address bus. figure 12-5 eprom programming circuit for bootstrap mode osc1 osc2 mc68hc705f8 vpp 10m 22p 3.58mhz v pp +5v 470 470 program/verify verify 27256 ce oe vpp v cc qa qb qc qd r clr hc393 qa qb qc qd r clr hc393 qa qb qc qd r clr hc393 qa qb qc qd r clr hc393 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 d0 d1 d2 d3 d4 d5 d6 d7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb3 pb4 pb5 +5v pb0 pb1 pb2 +5v pb6 pb7 reset irq1 22p tcap 1n914 1n914 1 m + 1k 100k reset 0.01 m +5v vss vdd 10k 10k 10k open - program & verify closed - verify s1 s4 tpg 109
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mc68hc05f8 motorola 13-1 electrical specifications 13 13 electrical specifications this section contains the electrical speci?ations for the mc68hc05f8. 13.1 maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vin and vout be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either v ss or v dd ). 13.2 thermal characteristics voltages referenced to v ss ratings symbol value unit supply voltage v dd ?.3 to +7.0 v input voltage v in v ss ?.3 to v dd +0.3 v irq v in v ss ?.3 to 2xv dd +0.3 v current drain per pin excluding v dd and v ss i d 25 ma operating temperature t a 0 to 70 c storage temperature range t stg ?5 to +150 c characteristics symbol value unit thermal resistance - plastic 56-pin sdip package - plastic 64-pin qfp package q ja q ja 50 50 c/w c/w tpg 111
motorola 13-2 mc68hc05f8 electrical specifications 13 13.3 dc electrical characteristics table 13-1 dc electrical characteristics for 5v operation v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c characteristics symbol minimum typical maximum unit output voltage i load ?0 m a i load +10 m a v oh v ol v dd -0.1 0.1 v v output high voltage (i load =1.6ma) pa4-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcmp, tnx v oh v dd -0.8 v output low voltage (i load =1.6ma) pa4-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcmp, tnx v ol 0.4 v input high voltage pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcap, irq1 , irq2 , reset , osc1 v ih 0.7xv dd ? dd v input low voltage pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcap, irq1 , irq2 , reset , osc1 v il v ss 0.2xv dd v data retention mode v rm 2.0 v supply current run wait stop i dd 3.8 1.1 0.9 5 2 1.5 ma ma m a i/o ports high-z leakage current pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7 i il 10 m a input current tcap, irq1 , irq2 , reset , decoin, osc1 i in 1 m a capacitance ports (as input or output), reset , irq1 , irq2 , tcap, osc1 c out c in 12 8 pf port c high current sinking capability (for 1v saturation) i sk ?0ma tpg 112
mc68hc05f8 motorola 13-3 electrical specifications 13 table 13-2 dc electrical characteristics for 2.7v operation v dd =2.7vdc 10%, v ss =0vdc, temperature range=0 to 70 c characteristics symbol minimum typical maximum unit output voltage i load ?0 m a i load +10 m a v oh v ol v dd -0.1 0.1 v v output high voltage (i load =1.6ma) pa4-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcmp, tnx v oh v dd -0.3 v output low voltage (i load =1.6ma) pa4-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcmp, tnx v ol 0.3 v input high voltage pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcap, irq1 , irq2 , reset , osc1 v ih 0.7xv dd ? dd v input low voltage pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7, tcap, irq1 , irq2 , reset , osc1 v il v ss 0.2xv dd v data retention mode v rm 2.0 v supply current run wait stop i dd 1.5 450 360 tbd tbd tbd ma m a na i/o ports high-z leakage current pa0-pa5, pb0-pb7, pc0-pc7, pd0-pd7 i il 10 m a input current tcap, irq1 , irq2 , reset , decoin, osc1 i in 1 m a capacitance ports (as input or output), reset , irq1 , irq2 , tcap, osc1 c out c in 12 8 pf port c high current sinking capability (for 1v saturation) i sk ?0ma tpg 113
motorola 13-4 mc68hc05f8 electrical specifications 13 13.4 dtmf/melody generator electrical characteristics table 13-3 electrical speci?ation of sine wave tones at toneout output (including dtmf) characteristics minimum typical maximum unit operating voltage 2.5 5.5 v tone output level: low group - row high group - column frequency deviation (dtmf) frequency deviation (melody) tone output dc level high group pre-emphasis 0.125 0.158 ?.65 ?.5 0.45 1 0.15 0.192 0.50 2 0.16 0.205 +0.65 +1.5 0.55 3 v rms v rms % % v dd db table 13-4 electrical speci?ation of square wave tones at toneout output characteristics minimum typical maximum unit operating voltage 2.5 5.5 v tone output level: low group - row high group - column frequency deviation (melody) tone output dc level (+0.5 v p-p value) 0.19 0.24 ?.5 0.45 0.21 0.27 0.50 0.24 0.30 +1.5 0.55 v p-p v p-p % v dd table 13-5 electrical speci?ation of tonex at tonex output characteristics minimum typical maximum unit tone output level (square wave) frequency deviation tone output dc level ?.5 0.45 v dd 0.50 1.5 0.55 v p-p % v dd tpg 114
mc68hc05f8 motorola 13-5 electrical specifications 13 13.5 control timing table 13-6 control timing for 5v operation (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation crystal option external clock option f osc dc 3.58 3.58 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 1.8 1.8 mhz mhz processor cycle time t cyc 556 ns crystal oscillator start-up time t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 0.25 4 sec timer a resolution (1) input capture pulse width input capture pulse period t aresl t th , t tl t tltl 4 125 (2) 64 t cyc ns t cyc timer b resolution t bresl 2.25 18 m s interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (3) ? cyc (1) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (2) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (3) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . tpg 115
motorola 13-6 mc68hc05f8 electrical specifications 13 table 13-7 control timing for 2.7v operation (v dd =3.3vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation crystal option external clock option f osc dc 3.58 3.58 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 1.8 1.8 mhz mhz processor cycle time t cyc 556 ns crystal oscillator start-up time t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 0.25 4 sec timer a resolution (1) input capture pulse width input capture pulse period t aresl t th , t tl t tltl 4 250 (2) 64 t cyc ns t cyc timer b resolution t bresl 2.25 18 m s interrupt pulse width (edge-triggered) t ilih 250 ns interrupt pulse period t ilil (3) ? cyc (1) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (2) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (3) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . tpg 116
mc68hc05f8 motorola 13-7 electrical specifications 13 13.6 programming operation electrical characteristics v dd =5.0vdc 5%, v ss =0vdc, temperature range=20 to 30 c) characteristics symbol minimum typical maximum unit programming voltage v pp 13 14 15 v v pp supply current v pp =v dd v pp =14v i pp 3 4 4 5 8 m a ma programming bus frequency f bus 1.70 1.79 1.89 mhz bootstrap programming mode voltage (irq1 pin, i in =100 m a max.) v ihtp 9.0 10.0 10.3 v tpg 117
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mc68hc05f8 motorola 14-1 mechanical specifications 14 14 mechanical specifications this section provides the mechanical dimension for the 56-pin sdip and 64-pin qfp packages for the mc68hc05f8. 14.1 56-pin sdip package figure 14-1 56-pin sdip mechanical dimensions 1 56 c k n g d f l m plane seating p j dim. min. max. notes dim. min. max. a 51.69 52.45 1. dimensions and tolerancing per ansi y 14.5 1982. 2. all dimensions in mm. 3. dimension l to centre of lead when formed parallel. 4. dimensions a and b do not include mould ?sh. allowable mould ?sh is 0.25 mm. h 7.62 bsc b 13.72 14.22 j 0.20 0.38 c 3.94 5.08 k 2.92 3.43 d 0.36 0.56 l 15.24 bsc e 0.89 bsc m 0 15 f 0.81 1.17 n 0.51 1.02 g 1.778 bsc p 1.78 2.29 case no. 859-01 56 lead sdip 28 29 0.25 m ta s - a - - b - - t - h e 0.25 m tb s tpg 119
motorola 14-2 mc68hc05f8 mechanical specifications 14 14.2 64-pin qfp package figure 14-2 64-pin qfp mechanical dimensions 64 lead qfp 0.20 m c a ?b s d s l 33 48 16 1 32 17 49 64 - b - b v 0.05 a ?b - d - a s 0.20 m h a ?b s d s l - a - detail ? b b - a, b, d - p detail ? f n j d section b? base metal g h e c -c- m detail ? m -h- datum plane seating plane u t r q k w x dim. min. max. notes dim. min. max. a 13.90 14.10 1. datum plane ??is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. datums ?? ??and ??to be determined at datum plane ?? 3. dimensions s and v to be determined at seating plane ?? 4. dimensions a and b do not include mould protrusion. allowable mould protrusion is 0.25mm per side. dimensions a and b do include mould mismatch and are determined at datum plane ?? 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 6. dimensions and tolerancing per ansi y 14.5m, 1982. 7. all dimensions in mm. m5 10 b 13.90 14.10 n 0.130 0.170 c 2.067 2.457 p 0.40 bsc d 0.30 0.45 q 2 8 e 2.00 2.40 r 0.13 0.30 f 0.30 s 16.20 16.60 g 0.80 bsc t 0.20 ref h 0.067 0.250 u 9 15 j 0.130 0.230 v 16.20 16.60 k 0.50 0.66 w 0.042 nom l 12.00 ref x 1.10 1.30 0.20 m c a ?b s d s 0.05 a ?b 0.20 m h a ?b s d s 0.20 m c a ?b s d s case no. 840c tpg 120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 general description pin descriptions memory and registers resets interrupts timers serial peripheral interface manchester encoder/decoder dtmf/melody generator cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications tpg 121
1 2 3 4 5 6 7 8 9 10 11 12 13 14 general description pin descriptions memory and registers resets interrupts timers serial peripheral interface manchester encoder/decoder dtmf/melody generator cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications tpg 122
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2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 !motorola MC68HC05F8D/h how to reach us: mfax: rmfax0@email.sps.mot.com ?touchtone (602) 244-6609 internet: http://design-net.com usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 japan: nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 hong kong: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298

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